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STM32F427ZGY6XXX

Description
32-BIT, FLASH, 180MHz, RISC MICROCONTROLLER, PBGA143, 4.521X 5.547 MM, 0.40 MM PITCH, ROHS COMPLIANT, WLCSP-143
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size3MB,240 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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STM32F427ZGY6XXX Overview

32-BIT, FLASH, 180MHz, RISC MICROCONTROLLER, PBGA143, 4.521X 5.547 MM, 0.40 MM PITCH, ROHS COMPLIANT, WLCSP-143

STM32F427ZGY6XXX Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid1352370015
package instructionVFBGA, BGA143,11X13,16
Reach Compliance Codecompliant
ECCN code3A991.A.2
Has ADCYES
Address bus width26
bit size32
boundary scanYES
CPU seriesCORTEX-M4
maximum clock frequency26 MHz
DAC channelYES
DMA channelYES
External data bus width16
FormatFLOATING POINT
Integrated cacheNO
JESD-30 codeR-PBGA-B143
length5.547 mm
low power modeYES
Number of DMA channels2
Number of external interrupt devices16
Number of I/O lines114
Number of serial I/Os4
Number of terminals143
Number of timers15
On-chip data RAM width8
On-chip program ROM width8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Encapsulate equivalent codeBGA143,11X13,16
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
RAM (bytes)266240
rom(word)1048576
ROM programmabilityFLASH
Maximum seat height0.585 mm
speed180 MHz
Maximum slew rate100 mA
Maximum supply voltage3.6 V
Minimum supply voltage1.7 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.4 mm
Terminal locationBOTTOM
width4.521 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC
STM32F427xx STM32F429xx
32b Arm
®
Cortex
®
-M4 MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB
OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera & LCD-TFT
Datasheet
-
production data
Features
Core: Arm
®
32-bit Cortex
®
-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
Memories
– Up to 2 MB of Flash memory organized into
two banks allowing read-while-write
– Up to 256+4 KB of SRAM including 64-KB
of CCM (core coupled memory) data RAM
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, Compact
Flash/NOR/NAND memories
LCD parallel interface, 8080/6800 modes
LCD-TFT controller with fully programmable
resolution (total width up to 4096 pixels, total
height up to 2048 lines and pixel clock up to
83 MHz)
Chrom-ART Accelerator™ for enhanced
graphic content creation (DMA2D)
Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
Low power
– Sleep, Stop and Standby modes
– V
BAT
supply for RTC, 20×32 bit backup
registers + optional 4 KB backup SRAM
3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
2×12-bit D/A converters
General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 180 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
LQFP100 (14 × 14 mm) UFBGA176 (10 x 10 mm)
LQFP144 (20 × 20 mm) UFBGA169 (7 × 7 mm)
LQFP176 (24 × 24 mm)
TFBGA216 (13 x 13 mm)
LQFP208 (28 x 28 mm)
WLCSP143
Debug mode
– SWD & JTAG interfaces
– Cortex-M4 Trace Macrocell™
Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 90 MHz
– Up to 166 5 V-tolerant I/Os
Up to 21 communication interfaces
– Up to 3 × I
2
C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to 6 SPIs (45 Mbits/s), 2 with muxed
full-duplex I
2
S for audio class accuracy via
internal audio PLL or external clock
– 1 x SAI (serial audio interface)
– 2 × CAN (2.0B Active) and SDIO interface
Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
8- to 14-bit parallel camera interface up to
54 Mbytes/s
True random number generator
CRC calculation unit
RTC: subsecond accuracy, hardware calendar
96-bit unique ID
January 2018
This is information on a product in full production.
DocID024030 Rev 10
1/239
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