Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
DESCRIPTION
Monolithic temperature and
overload protected logic level power
MOSFET in a 3 pin plastic
envelope, intended as a general
purpose switch for automotive
systems and other applications.
BUK100-50GL
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
D
T
j
R
DS(ON)
PARAMETER
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
V
IS
= 5 V
MAX.
50
13.5
40
150
125
UNIT
V
A
W
˚C
mΩ
APPLICATIONS
General controller for driving
lamps
motors
solenoids
heaters
FEATURES
Vertical power DMOS output
stage
Low on-state resistance
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Low operating input current
ESD protection on input pin
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V
CLAMP
INPUT
RIG
POWER
MOSFET
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - TO220AB
PIN
1
2
3
tab
input
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
D
TOPFET
I
P
1 23
S
November 1996
1
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
V
DSS
V
IS
I
D
I
D
I
DRM
P
D
T
stg
T
j
T
sold
PARAMETER
Continuous off-state drain source
voltage
1
Continuous input voltage
Continuous drain current
Continuous drain current
Repetitive peak on-state drain current
Total power dissipation
Storage temperature
Continuous junction temperature
2
Lead temperature
CONDITIONS
V
IS
= 0 V
-
T
mb
≤
25 ˚C; V
IS
= 5 V
T
mb
≤
100 ˚C; V
IS
= 5 V
T
mb
≤
25 ˚C; V
IS
= 5 V
T
mb
≤
25 ˚C
-
normal operation
during soldering
MIN.
-
0
-
-
-
-
-55
-
-
BUK100-50GL
MAX.
50
6
13.5
8.5
54
40
150
150
250
UNIT
V
V
A
A
A
W
˚C
˚C
˚C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.
SYMBOL
V
ISP
V
DDP(T)
V
DDP(P)
P
DSM
PARAMETER
Protection supply voltage
3
Over temperature protection
Protected drain source supply voltage V
IS
= 5 V
Short circuit load protection
Protected drain source supply voltage
4
V
IS
= 5 V
Instantaneous overload dissipation
T
mb
= 25 ˚C
-
-
-
50
35
0.6
V
V
kW
CONDITIONS
for valid protection
MIN.
4
MAX.
-
UNIT
V
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL
I
DROM
E
DSM
E
DRM
PARAMETER
Repetitive peak clamping current
Non-repetitive clamping energy
Repetitive clamping energy
CONDITIONS
V
IS
= 0 V
T
mb
≤
25 ˚C; I
DM
= 15 A;
V
DD
≤
20 V; inductive load
T
mb
≤
95 ˚C; I
DM
= 4 A;
V
DD
≤
20 V; f = 250 Hz
MIN.
-
-
-
MAX.
15
200
20
UNIT
A
mJ
mJ
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model;
C = 250 pF; R = 1.5 kΩ
MIN.
-
MAX.
2
UNIT
kV
1
Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2
A higher T
j
is allowed as an overload condition but at the threshold T
j(TO)
the over temperature trip operates to protect the switch.
3
The input voltage for which the overload protection circuits are functional.
4
The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed V
DDP(P)
maximum.
For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
November 1996
2
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Thermal resistance
R
th j-mb
R
th j-a
Junction to mounting base
Junction to ambient
-
in free air
-
-
CONDITIONS
MIN.
BUK100-50GL
TYP.
MAX.
UNIT
2.5
60
3.1
-
K/W
K/W
STATIC CHARACTERISTICS
T
mb
= 25 ˚C unless otherwise specified
SYMBOL
V
(CL)DSS
V
(CL)DSS
I
DSS
I
DSS
I
DSS
R
DS(ON)
PARAMETER
Drain-source clamping voltage
Drain-source clamping voltage
CONDITIONS
V
IS
= 0 V; I
D
= 10 mA
MIN.
50
-
-
-
-
-
TYP.
-
-
0.5
1
10
85
MAX.
-
70
10
20
100
125
UNIT
V
V
µA
µA
µA
mΩ
V
IS
= 0 V; I
DM
= 1 A; t
p
≤
300
µs;
δ ≤
0.01
Zero input voltage drain current V
DS
= 12 V; V
IS
= 0 V
Zero input voltage drain current V
DS
= 50 V; V
IS
= 0 V
Zero input voltage drain current V
DS
= 40 V; V
IS
= 0 V; T
j
= 125 ˚C
Drain-source on-state
V
IS
= 5 V; I
DM
= 7.5 A; t
p
≤
300
µs;
resistance
δ ≤
0.01
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.
SYMBOL
E
DS(TO)
t
d sc
T
j(TO)
PARAMETER
Short circuit load protection
1
Overload threshold energy
Response time
CONDITIONS
T
mb
= 25 ˚C; L
≤
10
µH
V
DD
= 13 V; V
IS
= 5 V
V
DD
= 13 V; V
IS
= 5 V
MIN.
-
-
150
TYP.
0.2
0.8
-
MAX.
-
-
-
UNIT
J
ms
˚C
Over temperature protection
Threshold junction temperature V
IS
= 5 V; from I
D
≥
1 A
2
INPUT CHARACTERISTICS
T
mb
= 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL
V
IS(TO)
I
IS
V
ISR
V
ISR
I
ISL
V
(BR)IS
R
IG
PARAMETER
Input threshold voltage
Input supply current
Protection reset voltage
3
Protection reset voltage
Input supply current
Input clamp voltage
Input series resistance
CONDITIONS
V
DS
= 5 V; I
D
= 1 mA
V
IS
= 5 V; normal operation
T
j
= 150 ˚C
V
IS
= 5 V; protection latched
I
I
= 10 mA
to gate of power MOSFET
MIN.
1.0
-
2.0
1.0
0.5
6
-
TYP.
1.5
0.2
2.6
-
1.2
-
4
MAX.
2.0
0.35
3.5
-
2.0
-
-
mA
V
kΩ
UNIT
V
mA
V
1
The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
P
DSM
, which is always the case when V
DS
is less than V
DSP
maximum. Refer to OVERLOAD PROTECTION LIMITING VALUES.
2
The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum I
D
ensures this condition.
3
The input voltage below which the overload protection circuits will be reset.
November 1996
3
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
TRANSFER CHARACTERISTICS
T
mb
= 25 ˚C
SYMBOL
g
fs
I
D(SC)
PARAMETER
Forward transconductance
Drain current
1
CONDITIONS
V
DS
= 10 V; I
DM
= 7.5 A t
p
≤
300
µs;
δ ≤
0.01
V
DS
= 13 V; V
IS
= 5 V
MIN.
5
-
BUK100-50GL
TYP.
9
25
MAX.
-
-
UNIT
S
A
SWITCHING CHARACTERISTICS
T
mb
= 25 ˚C. R
I
= 50
Ω
. Refer to waveform figures and test circuits.
SYMBOL
t
d on
t
r
t
d off
t
f
t
d on
t
r
t
d off
t
f
PARAMETER
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Turn-on delay time
Rise time
Turn-off delay time
Fall time
CONDITIONS
V
DD
= 13 V; V
IS
= 5 V
resistive load R
L
= 4
Ω
V
DD
= 13 V; V
IS
= 0 V
resistive load R
L
= 4
Ω
V
DD
= 13 V; V
IS
= 5 V
inductive load I
DM
= 3 A
V
DD
= 13 V; V
IS
= 0 V
inductive load I
DM
= 3 A
MIN.
-
-
-
-
-
-
-
-
TYP.
1.5
8
6
4.5
1.5
1
10
0.5
MAX.
-
-
-
-
-
-
-
-
UNIT
µs
µs
µs
µs
µs
µs
µs
µs
REVERSE DIODE LIMITING VALUE
SYMBOL
I
S
PARAMETER
Continuous forward current
CONDITIONS
T
mb
≤
25 ˚C; V
IS
= 0 V
MIN.
-
MAX.
13.5
UNIT
A
REVERSE DIODE CHARACTERISTICS
T
mb
= 25 ˚C
SYMBOL
V
SDS
t
rr
PARAMETER
Forward voltage
Reverse recovery time
CONDITIONS
I
S
= 15 A; V
IS
= 0 V; t
p
= 300
µs
not applicable
2
MIN.
-
-
TYP.
1.0
-
MAX.
1.5
-
UNIT
V
-
ENVELOPE CHARACTERISTICS
SYMBOL
L
d
L
d
L
s
PARAMETER
Internal drain inductance
Internal drain inductance
Internal source inductance
CONDITIONS
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
MIN.
-
-
-
TYP.
3.5
4.5
7.5
MAX.
-
-
-
UNIT
nH
nH
nH
1
During overload before short circuit load protection operates.
2
The reverse diode of this type is not intended for applications requiring fast reverse recovery.
November 1996
4
Rev 1.300
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50GL
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
10
Zth / (K/W)
BUK100-50GL
D=
0.5
1
0.2
0.1
0.05
0.1
0.02
P
D
t
p
D=
t
p
T
t
0
0
20
40
60
80
100
Tmb / C
120
140
0.01
1E-07
T
1E-05
1E-03
t/s
1E-01
1E+01
Fig.2. Normalised limiting power dissipation.
P
D
% = 100
⋅
P
D
/P
D
(25 ˚C) = f(T
mb
)
ID%
Normalised Current Derating
Fig.5. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
ID / A
BUK100-50GL
VIS / V =
120
110
100
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
6
5.5
5
4.5
4
3.5
3
2.5
0
4
8
12
16
VDS / V
20
24
28
32
0
20
40
60
80
Tmb / C
100
120
140
0
Fig.3. Normalised continuous drain current.
I
D
% = 100
⋅
I
D
/I
D
(25 ˚C) = f(T
mb
); conditions: V
IS
= 5 V
ID & IDM / A
D
S/I
VD
=
Fig.6. Typical output characteristics, T
j
= 25 ˚C.
ID = f(V
DS
); parameter V
IS
; t
p
= 250
µ
s & t
p
< t
d sc
ID / A
BUK100-50GL
VIS / V =
6
5.5
30
5
25
4.5
20
15
10
4
3.5
3
100
BUK100-50GL
tp =
10 us
100 us
1 ms
DC
10 ms
100 ms
40
35
N)
(O
DS
R
10
1
Overload protection characteristics not shown
0.1
1
10
VDS / V
100
5
0
0
1
2
VDS / V
3
4
5
Fig.4. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.7. Typical on-state characteristics, T
j
= 25 ˚C.
ID = f(V
DS
); parameter V
IS
; t
p
= 250
µ
s
November 1996
5
Rev 1.300
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