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BUK113-50DL

Description
PowerMOS transistor Logic level TOPFET
CategoryDiscrete semiconductor    The transistor   
File Size27KB,6 Pages
ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.)
Websitehttps://www.nxp.com/
Download Datasheet Parametric View All

BUK113-50DL Overview

PowerMOS transistor Logic level TOPFET

BUK113-50DL Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerPhilips Semiconductors (NXP Semiconductors N.V.)
package instruction,
Reach Compliance Codeunknow
ECCN codeEAR99
ConfigurationSingle
Maximum drain current (Abs) (ID)8 A
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-609 codee0
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)4 W
surface mountYES
Terminal surfaceTin/Lead (Sn/Pb)
Philips Semiconductors
Objective specification
PowerMOS transistor
Logic level TOPFET
DESCRIPTION
Monolithic overload protected logic
level power MOSFET in a surface
mount plastic envelope, intended as
a general purpose switch for
automotive systems and other
applications.
BUK113-50DL
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
D
T
j
R
DS(ON)
PARAMETER
Continuous drain source voltage
Drain current limiting
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
MIN.
-
4
-
-
-
MAX. UNIT
50
8
4
150
200
V
A
W
˚C
mΩ
APPLICATIONS
General controller for driving
lamps
small motors
solenoids
FEATURES
Vertical power DMOS output
stage
Overload protected up to
125˚C ambient
Overload protection by current
limiting and overtemperature
sensing
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V
CLAMP
INPUT
RIG
POWER
MOSFET
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT223
PIN
1
2
3
4
input
drain
source
drain (tab)
DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
D
TOPFET
I
P
1
2
3
S
January 1996
1
Rev 1.000
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