Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope available in
TO220AB and SOT404 . Using
’trench’ technology which features
very low on-state resistance. It is
intended for use in automotive and
general
purpose
switching
applications.
BUK95180-100A
BUK96180-100A
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 5 V
V
GS
= 10 V
MAX.
100
11
54
175
180
173
UNIT
V
A
W
˚C
mΩ
mΩ
PINNING
TO220AB & SOT404
PIN
1
2
3
DESCRIPTION
gate
drain
2
mb
tab
PIN CONFIGURATION
SYMBOL
d
g
3
SOT404
BUK96180-100A
source
1
tab/mb drain
1 2 3
TO220AB
BUK95180-100A
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
100
100
15
11
7.7
44
54
175
UNIT
V
V
V
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient(TO220AB)
Thermal resistance junction to
ambient(SOT404)
CONDITIONS
-
in free air
Minimum footprint, FR4
board
TYP.
-
60
50
MAX.
2.8
-
-
UNIT
K/W
K/W
K/W
May 2000
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
DS
= 100 V; V
GS
= 0 V;
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 5 A
V
GS
= 10 V; I
D
= 5 A
V
GS
= 4.5 V; I
D
= 5 A
T
j
= 175˚C
T
j
= 175˚C
MIN.
100
89
1
0.5
-
-
-
-
-
-
-
-
BUK95180-100A
BUK96180-100A
TYP.
-
-
1.5
-
-
0.05
-
2
165
-
152
170
MAX.
-
-
2.0
-
2.3
10
500
100
180
450
173
200
UNIT
V
V
V
V
V
µA
µA
nA
mΩ
mΩ
mΩ
mΩ
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
d
L
d
L
s
PARAMETER
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal drain inductance
Internal source inductance
CONDITIONS
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
-
-
-
-
-
-
-
-
-
-
-
TYP.
464
60
37
9
112
18
25
4.5
3.5
2.5
7.5
MAX.
619
72
50
20
157
27
38
-
-
-
-
UNIT
pF
pF
pF
ns
ns
ns
ns
nH
nH
nH
nH
V
DD
= 30 V; R
load
=1.2Ω;
V
GS
= 5 V; R
G
= 10
Ω
Measured from drain lead 6 mm
from package to centre of die
Measured from contact screw on
tab to centre of die(TO220AB)
Measured from upper edge of drain
tab to centre of die(SOT404)
Measured from source lead to
source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
I
F
= 5 A; V
GS
= 0 V
I
F
= 11 A; V
GS
= 0 V
I
F
= 11 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
-
-
-
-
-
TYP.
-
-
0.85
1.1
49
0.13
MAX.
11
44
1.2
-
-
-
UNIT
A
A
V
V
ns
µC
May 2000
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS1
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 5.5 A; V
DD
≤
25 V;
V
GS
= 5 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
BUK95180-100A
BUK96180-100A
TYP.
-
MAX.
1.5
UNIT
mJ
!
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
100
ID/A
RDS(ON)=VSD/ID
10
DC
1
0
20
40
60
80 100
Tmb / C
120
140
160
180
0.1
1
10
VSD/V
100
1000
Fig.1. Normalised power dissipation.
PD% = 100⋅P
D
/P
D 25 ˚C
= f(T
mb
)
ID%
Normalised Current Derating
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
120
110
100
90
80
70
60
50
40
30
20
10
0
Zth/(K/W)
10
0.5
1
0.2
0.1
0.05
0.1
0.02
0.01
0
0
20
40
60
80
100
Tmb / C
120
140
160
180
0.001
1E-07
1E-05
t/s
1E-03
1E-01
1E+01
Fig.2. Normalised continuous drain current.
ID% = 100⋅I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
1
For maximum permissible repetive avalanche current see fig.18.
May 2000
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
25
ID/A
20
15
10
5
0
0
2
4
VDS/V
6
VGS/V =
10.0
5.0
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
8
10
12
ID/A
10
8
6
4
2
0
0
2
4
VGS/V
6
8
Tj/C= 175
25
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
240
220
200
180
160
140
120
100
RDS(ON)/mOhm
3.0
3.2
3.4
3.6
3.8
4.0
5.0
gfs/S
16
14
12
10
8
6
4
2
0
2
4
6
ID/A
8
10
12
0
2
4
6 ID/A 8
10
12
14
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.9. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Rds(on) normalised to 25degC
240
230
220
210
200
190
180
170
160
150
RDS(ON) Ohm
3
a
2.5
2
1.5
1
3
4
5
6
7
VGS/V
8
9
10
0.5
-100
-50
0
50
100
Tmb / degC
150
200
Fig.7. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(V
GS
); conditions: I
D
= 25 A;
Fig.10. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
May 2000
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
2.5
VGS(TO) / V
max.
5
VGS / V
4
2
typ.
1.5
min.
1
3
2
1
0.5
0
0
-100
-50
0
50
Tj / C
100
150
200
0
2
4
QG / nC
6
8
10
Fig.11. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.14. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 25 A; parameter V
DS
1E-01
Sub-Threshold Conduction
15
IF/A
1E-02
10
1E-03
2%
typ
98%
Tj/C= 150
1E-04
25
5
1E-05
0
1E-05
0.0
0
0.5
1
1.5
2
2.5
3
0.2
0.4
0.6
VSDS/V
0.8
1.0
1.2
Fig.12. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.15. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
WDSS%
Capacitance / pF
1200
1000
800
600
400
200
0
0.01
Coss
Crss
100
Ciss
120
110
100
90
80
70
60
50
40
30
20
10
0
0.1
1
VDS/V
10
20
40
60
80
100
120
Tmb / C
140
160
180
Fig.13. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.16. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 75 A
May 2000
5
Rev 1.100
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