STPTIC-27L2
Parascan™ tunable integrated capacitor
Datasheet
-
production data
Description
The ST integrated tunable capacitor offers
excellent RF performance, low power
consumption and high linearity required in
adaptive RF tuning applications. The fundamental
building block of PTIC is a tunable material called
Parascan
™
, which is a version of barium
strontium titanate (BST) developed by Paratek
Microwave.
BST capacitors are tunable capacitors intended
for use in mobile phone application and dedicated
to RF tunable applications. These tunable
capacitors are controlled through an extended
bias voltage ranging from 1 to 24 V. The
implementation of BST tunable capacitors in
mobile phones enables significant improvement
in terms of radiated performance making the
performance almost insensitive to the external
environment.
Figure 1. PTIC functional block diagram
Features
•
High power capability
•
5:1 tuning range
•
Higher linearity (48x)
•
High quality factor (Q)
•
Low leakage current
•
Compatible with high voltage control IC
(STHVDAC series)
•
Available in WLCSP package 0.75 x 1.00 x 0.3
mm
•
ECOPACK
®
2 compliant component
Benefit
•
RF tunable passive implementation in mobile
phones to optimize antenna radiated
performance
Applications
•
Cellular antenna open loop tunable matching
network in multi-band GSM/WCDMA/LTE
mobile phone
•
Open loop tunable RF filters
TM: Parascan is a trademark of Paratek Microwave Inc.
December 2015
This is information on a product in full production.
DocID028611 Rev 1
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www.st.com
Electrical characteristics
STPTIC-27L2
1
Electrical characteristics
Table 1. Absolute maximum ratings (limiting values)
Symbol
P
IN
V
ESD(HBM)
V
ESD(MM)
T
device
T
stg
V
x
Parameter
Input peak power RF
IN
(CW mode)/all RF ports
Human body model, JESD22-A114-B, all I/O
Machine model, JESD22-A115-A, all I/O
Device temperature
Storage temperature
Bias voltage
Rating
+40
Class 1B
(1)
100
+125
°C
-55 to +150
25
V
Unit
dBm
V
V
1. Class 1B defined as passing 500 V, but fails after exposure to 1000V ESD pulse.
Table 2. Recommended operating conditions
Rating
Symbol
P
IN
F
OP
T
device
T
OP
V
BIAS
RF input power
Operating frequency
Device temperature
Operating temperature
Bias voltage
-30
1
700
Parameter
Min.
Typ.
+33
Max.
+39
2700
+100
°C
+85
24
V
dBm
MHz
Unit
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DocID028611 Rev 1
STPTIC-27L2
Electrical characteristics
Table 3. Representative performance (T
amb
= 25 °C otherwise specified)
Value
Symbol
C
1V
C
2V
C
20V
C
24V
∆C
I
L
Q
LB
Q
HB
Parameter
capacitance at 1 V bias
capacitance at 2 V bias
capacitance at 20V bias
capacitance at 24 V bias
Tuning range
Leakage current
Quality factor
Quality factor
STPTIC-27L2
STPTIC-27L2
STPTIC-27L2
STPTIC-27L2
Conditions
Min. Typ. Max.
2.8
2.43
3.2
2.7
3.58
2.97
Unit
pF
pF
pF
pF
0.63 0.69 0.75
0.56 0.61 0.66
5/1
100
50
35
60
80
80
-70
-80
-65
-75
-65
-55
-85
-45
-70
-70
50
55
40
Ratio between C
1V
/C
24V(1)
Measured with V
bias
= 24 V
Measured at 700 MHz at 2 V
Measured at 2700 MHz at 2 V
V
bias
= 1 V
(2)(4)
nA
IP3
Third order intercept point V
bias
= 24 V
(2)(4)
V
bias
= 20 V
(2)(4)
V
bias
= 1 V
(3)(4)
V
bias
= 24 V
(3)(4)
V
bias
= 20 V
(3)(4)
V
bias
= 1 V
(3)(4)
V
bias
= 24 V
(3)(4)
V
bias
= 20 V
(3)(4)
Average for any transition between C
min
to C
max(5)
Average transition between C
max
to C
min
(5)
dBm
H2
Second harmonic
dBm
H3
Third harmonic
dBm
t
T
Transition time
µs
30
1. Measured at low frequency
2. F
1
= 894 MHz, F
2
= 849 MHz, P
1
= +25 dBm, P
2
= +25 dBm, 2f
1
- f
2
= 939 MHz
3. 850 MHz, P
in
= +34 dBm, CW
4. IP3 and harmonics are measured in the shunt configuration in a 50
Ω
environment
5. One or both of RF
in
and RF
out
must be connected to DC ground, using the HVDAC turbo mode
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Electrical characteristics
STPTIC-27L2
Figure 2. Capacitance variation versus bias
voltage
Figure 3. Quality factor versus frequency
Figure 4. Harmonic power versus bias voltage
(series)
Figure 5. Harmonic power versus bias voltage
(shunt)
Figure 6. Third order intercept point (IP3)
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STPTIC-27L2
Package information
2
Package information
•
•
Epoxy meets UL94, V0
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at:
www.st.com.
ECOPACK
®
is an ST trademark.
2.1
Flip-Chip package information
Figure 7. Flip-Chip package outline
The land pattern below is recommended for soldering the STPTIC-G2 on PCB.
NC stands for No Connect, this pad must not be connected on application board. Please
leave this pad floating.
Table 4. Flip-Chip package dimensions
Dimensions (in microns)
STPTIC-27L2
Tolerance
A1
1000
±30
A2
750
±30
B1
140
±15
B2
500
±10
B4
360
±15
C1
105
±15
C2
540
±10
D1
225
±20
D2
90
±20
D3
315
±40
E1
125
±20
E2
165
±20
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