STPTIC-33G2
Parascan™ tunable integrated capacitor
Datasheet
-
production data
Description
The ST integrated tunable capacitor offers
excellent RF performance, low power
consumption and high linearity required in
adaptive RF tuning applications. The fundamental
building block of PTIC is a tunable material called
Parascan
™
, which is a version of barium
strontium titanate (BST) developed by Paratek
Microwave.
BST capacitors are tunable capacitors intended
for use in mobile phone application and dedicated
to RF tunable applications. These tunable
capacitors are controlled through an extended
bias voltage ranging from 1 to 24 V. The
implementation of BST tunable capacitor in
mobile phones enables significant improvement
in terms of radiated performance making the
performance almost insensitive to the external
environment.
Figure 1. PTIC functional block diagram
Features
•
High power capability
•
5:1 tuning range
•
High linearity
•
High quality factor (Q)
•
Low leakage current
•
Compatible with high voltage control IC
(STHVDAC series)
•
Available in wafer level chip scale package:
– WLCSP package 0.61 x 0.66 x 0.3 mm
•
ECOPACK
®
2 compliant component
Benefit
•
RF tunable passive implementation in mobile
phones to optimize antenna radiated
performance
Applications
•
Cellular antenna open loop tunable matching
network in multi-band GSM/WCDMA/LTE
mobile phone
•
Open loop tunable RF filters
TM: Parascan is a trademark of Paratek Microwave Inc.
July 2015
This is information on a product in full production.
DocID028149 Rev 1
1/11
www.st.com
Electrical characteristics
STPTIC-33G2
1
Electrical characteristics
Table 1. Absolute maximum ratings (limiting values)
Symbol
P
IN
V
ESD(HBM)
V
ESD(MM)
T
device
T
stg
V
x
Parameter
Input peak power RF
IN
(CW mode)/all RF ports
Human body model, JESD22-A114-B, all I/O
Machine model, JESD22-A115-A, all I/O
Device temperature
Storage temperature
Bias voltage
Rating
+40
Class 1B
(1)
100
+125
-55 to +150
25
Unit
dBm
V
V
°C
V
1. Class 1B defined as passing 500 V, but fails after exposure to 1000V ESD pulse.
Table 2. Recommended operating conditions
Rating
Symbol
P
IN
F
OP
T
device
T
OP
V
BIAS
RF input power
Operating frequency
Device temperature
Operating temperature
Bias voltage
-30
1
700
Parameter
Min.
Typ.
+33
2700
+100
+85
24
Max.
dBm
MHz
°C
V
Unit
2/11
DocID028149 Rev 1
STPTIC-33G2
Electrical characteristics
Table 3. Representative performance (T
amb
= 25 °C otherwise specified)
Value
Symbol
C
1V
C
2V
C
24V
ΔC
I
L
Q
LB
Q
HB
IP3
Parameter
capacitor at 1 V bias
capacitor at 2 V bias
capacitor at 24 V bias
Tuning range
Leakage current
Quality factor
Quality factor
Third order intercept point
STPTIC-33G2
STPTIC-33G2
STPTIC-33G2
Ratio between C
1V
/C
24V(1)
Measured with V
bias
= 24 V
Measured at 700 MHz at 2 V
Measured at 2700 MHz at 2 V
V
bias
= 1 V
(2)(4)
V
bias
= 24 V
(2)(4)
V
bias
= 1 V
(3)(4)
V
bias
= 24 V
(3)(4)
V
bias
= 1 V
(3)(4)
V
bias
= 24 V
(3)(4)
Average for any transition between C
min
to C
max(5)
Average transition between C
max
to C
min
(5)
55
35
52
65
50
60
75
-65
-75
-35
-65
40
20
-30
-45
dBm
Conditions
Min
3.43
Typ Max
3.9
3.3
0.63 0.69 0.75
5/1
100
nA
4.37
pF
pF
pF
Unit
H2
Second harmonic
dBm
H3
Third harmonic
dBm
t
T
Transition time
µs
1. Measured at low frequency
2. F
1
= 894 MHz, F
2
= 849 MHz, P
1
= +25 dBm, P
2
= +25 dBm, 2f
1
- f
2
= 939 MHz
3. 850 MHz, P
in
= +34 dBm
4. IP3 and harmonics are measured in the shunt configuration in a 50
Ω
environment
5. One or both of RF
in
and RF
out
must be connected to DC ground, using the HVDAC turbo mode
DocID028149 Rev 1
3/11
11
Electrical characteristics
STPTIC-33G2
Figure 2. Capacitor variation versus bias
voltage
Figure 3. Quality factor versus frequency
Figure 4. Harmonic power versus bias voltage
(series)
Figure 5. Harmonic power versus bias voltage
(shunt)
Figure 6. Third order intercept point (IP3)
4/11
DocID028149 Rev 1
STPTIC-33G2
Package information
2
Package information
•
•
Epoxy meets UL94, V0
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at:
www.st.com.
ECOPACK
®
is an ST trademark.
2.1
Flip-Chip package information
Figure 7. Flip-Chip package outline
The land pattern below is recommended for soldering the STPTIC-G2 on PCB.
NC stands for No Connect, this pad must not be connected on application board. Please
leave this pad floating.
Table 4. Flip-Chip package dimensions
Dimensions (micron)
STPTIC-15/27/33/39/47G2
STPTIC-56G2
STPTIC-68G2
STPTIC-82G2
Tolerance
A1
640
710
780
880
±30
±30
±15
±10
590
120
400
A2
B1
B2
B4
120
190
260
360
±15
±15
±10
±20
±20
±40
±20
±20
85
420
200
90
290
125
165
C1
C2
D1
D2
D3
E1
E2
DocID028149 Rev 1
5/11
11
京公网安备 11010802033920号
EEWORLD
