INTEGRATED CIRCUITS
SCN2652/SCN68652
Multi-protocol communications controller
(MPCC)
Product specification
IC19 Data Handbook
1995 May 01
Philips
Semiconductors
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
DESCRIPTION
The SCN2652/68652 Multi-Protocol Communications Controller
(MPCC) is a monolithic n-channel MOS LSI circuit that formats,
transmits and receives synchronous serial data while supporting
bit-oriented or byte control protocols. The chip is TTL compatible,
operates from a single +5V supply, and can interface to a processor
with an 8 or 16-bit bidirectional data bus.
FEATURES
•
DC to 2Mbps data rate
•
Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC
•
Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)
•
Programmable operation
–
8 or 16-bit tri-state data bus
–
Error control – CRC or VRC or none
–
Character length – 1 to 8 bits for BOP or 5 to 8 bits for BCP
–
SYNC or secondary station address comparison for BCP-BOP
–
Idle transmission of SYNC/FLAG or MARK for BCP-BOP
APPLICATIONS
•
Intelligent terminals
•
Line controllers
•
Network processors
•
Front end communications
•
Remote data concentrators
•
Communication test equipment
•
Computer to computer links
•
Automatic detection and generation of special BOP control
sequences, i.e., FLAG, ABORT, GA
•
Zero insertion and deletion for BOP
•
Short character detection for last BOP data character
•
SYNC generation, detection, and stripping for BCP
•
Maintenance mode for self-testing
•
TTL compatible
•
Single +5V supply
PIN CONFIGURATION
INDEX
CORNER
CE
RxC
RxSI
S/F
RxA
RxDA
RxSA
RxE
1
2
3
4
5
6
7
8
40 MM
39 TxC
38 TxSQ
37 TxE
36 TxU
35 TxBE
17
34 TxA
33 RESET
32 V
CC
DIP
31 DB00
30 DB01
29 DB02
28 DB03
27 DB04
26 DB05
25 DB06
24 DB07
23 DBEN
22 BYTE
21 A0
TOP VIEW
NOTE: DB00 is least significant bit, highest number
(that is, DB15, A2) is most significant bit.
18
TOP VIEW
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
CE
RxC
RxSI
S/F
RxA
RxDA
RxSA
RxE
GND
DB08
NC
DB09
DB10
DB11
DB12
DB13
DB14
DB15
R/W
A2
A1
Pin Function
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
A0
BYTE
DBEN
DB07
DB06
DB05
DB04
DB03
DB02
DB01
NC
DB00
V
CC
RESET
TxA
TxBE
TxU
TxE
TxSQ
TxC
MM
28
29
PLCC
7
6
1
40
39
GND 9
DB08 10
DB09 11
DB10 12
DB11 13
DB12 14
DB13 15
DB14 16
DB15 17
R/W 18
A2 19
A1 20
SD00057
Figure 1. Pin Configuration
1995 May 01
2
853-1068 15179
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
ORDERING CODE
V
CC
= 5V +5%
PACKAGES
40-Pin Ceramic Dual In-Line Package (DIP)
40-Pin Plastic Dual In-Line Package (DIP)
44-Pin Square Plastic Lead Chip Carrier (PLCC)
Commercial
0°C to +70°C
SCN2652AC2F40 / SCN68652AC2F40
SCN2652AC2N40 / SCN68652AC2N40
SCN2652AC2A44 / SCN68652AC2A44
Contact Factory
Contact Factory
Industrial
-40°C to +85°C
DWG #
0590B
SOT129-1
SOT187-2
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
T
A
T
STG
Storage temperature
GND
3
PARAMETER
Operating ambient temperature
2
RATING
Note 4
–65 to +150
UNIT
°C
°C
V
CC
All inputs with respect to
–0.3 to +7
V
NOTES:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operation sections of this specification
is not implied.
2. For operating at elevated temperatures the device must be derated based on +150
°
C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
BLOCK DIAGRAM
16 BITS
DATA
BUS
BUFFER
16
PARAMETER CONTROL
SYNC/ADDRESS
REGISTER
PCSAR
8 BITS
PARAMETER
CONTROL
REGISTER
PCR
V
CC
GND
DB15–
DB00
RESET
MM
INTERNAL
BUS
RECEIVER
DATA/STATUS
REGISTER
RDSR
TRANSMITTER
DATA/STATUS
REGISTER
TDSR
A2–A0
BYTE
R/W
CE
DBEN
READ/
WRITE
LOGIC
AND
CONTROL
16
16
RECEIVER
LOGIC AND
CONTROL
TRANSMITTER
LOGIC AND
CONTROL
S/F
RxE
RxA
RxDA
RxSA
TxE
TxA
TxBE
TxU
RxC RxSI
TxC TxSO
SD00058
Figure 2. Block Diagram
1995 May 01
3
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
PIN DESCRIPTION
MNEMONIC
DB15–DB00
A2–A0
BYTE
CE
R/W
PIN NO.
17–10
24–31
19–21
22
1
18
TYPE
I/O
I
I
I
I
NAME AND FUNCTION
Data Bus:
DB07–DB00 contain bidirectional data while DB15–DB08 contain control and status
information to or from the processor. Corresponding bits of the high and low order bytes can be wire
OR’ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low.
Address Bus:
A2–A0 select internal registers. The four 16-bit registers can be addressed on a word or
byte basis. See Register Address section.
Byte:
Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies
16-bit data bus transfers.
Chip Enable:
A high input permits a data bus operation when DBEN is activated.
Read/Write:
R/W controls the direction of data bus transfer. When high, the data is to be loaded into the
addressed register. A low input causes the contents of the addressed register to be presented on the
data bus.
Data Bus Enable:
After A2–A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read,
the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is
loaded into the addressed register and TxBE will be reset if TDSR was addressed.
Reset:
A high level initializes all internal registers (to zero) and timing.
Maintenance Mode:
MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic
purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted.
Receiver Enable:
A high level input permits the processing of RxSI data. A low level disables the
receiver logic and initializes all receiver registers and timing.
Receiver Active:
RxA is asserted when the first data character of a message is ready for the processor.
In the BOP mode this character is the address. The received address must match the secondary station
address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR
13
) is set, the first
non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second
SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA
is reset by a low level at RxE.
Receiver Data Available:
RxDA is asserted when an assembled character is in RDSR
L
and is ready to
be presented to the processor. This output is reset when RDSR
L
is read.
Receiver Clock:
RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial
data into the RxSR from RxSI.
SYNC/FLAG:
S/F is asserted for one RxC clock time when a SYNC or FLAG character is detected.
Receiver Status Available:
RxSA is asserted when there is a zero to one transition of any bit in RDSR
H
except for RSOM. It is cleared when RDSR
H
is read.
Receiver Serial Input:
RxSI is the received serial data. Mark = ‘1’, space = ‘0’.
Transmitter Enable:
A high level input enables the transmitter data path between TDSR
L
and TxSO. At
the end of a message, a low level input causes TxSO = 1(mark) and TxA = 0 after the closing FLAG
(BOP) or last character (BCP) is output on TxSO.
Transmitter Active:
TxA is asserted after TSOM (TDSR
8
) is set and TxE is raised. This output will reset
when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO.
Transmitter Buffer Empty:
TxBE is asserted when theTDSR is ready to be loaded with new control
information or data. The processor should respond by loading theTDSR which resets TxBE.
Transmitter Underrun:
TxU is asserted during a transmit sequence when the service of TxBE has been
delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line
fill depends on PCSAR
11
. TxU is reset by RESET or setting of TSOM (TDSR
8
), synchronized by the
falling edge of TxC.
Transmitter Clock:
TxC (1X) provides timing for the transmitter logic. The positive going edge shifts
data out of the TxSR to TxSO.
Transmitter Serial Output:
TxSO is the transmitted serial data. Mark = ‘1’, space = ‘0’.
+5V:
Power supply.
Ground:
0V reference ground.
DBEN
RESET
MM
RxE
23
33
40
8
I
I
I
I
RxA
5
O
RxDA*
RxC
S/F
RxSA*
RxSI
TxE
6
2
4
7
3
37
O
I
O
O
I
I
TxA
TxBE*
34
35
O
O
TxU*
36
O
TxC
TxSO
V
CC
GND
39
38
32
9
I
O
I
I
*Indicates possible interrupt signal
1995 May 01
4
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Table 1.
Register Access
REGISTERS
NO. OF BITS
DESCRIPTION*
PCSAR
H
and PCR contain parameters common to the
receiver and transmitter. PCSAR
L
contains a programmable
SYNC character (BCP) or secondary station address (BOP).
RDSR
H
contains receiver status information.
RDSR
L
= RxDB contains the received assembled character.
TDSR
H
contains transmitter command and status
information. TDSRL = TxDB contains the character to be
transmitted
Addressable
PCSAR
PCR
RDSR
TDSR
Parameter control sync/
address register
Parameter control register
Receive data/status register
Transmit data/status register
16
8
16
16
Non-Addressable
CCSR
HSR
RxSR
TxSR
RxCRC
TxCRC
Control character shift register
Holding shift register
Receiver shift register
Transmitter shift register
Receiver CRC accumulation
register
Transmitter CRC generation
register
8
16
8
8
16
16
These registers are used for character assembly (CSSR
(CSSR,
HSR, RxSR), disassembly (TxSR), and CRC
,
),
y(
),
accumulation/generation (RxCRC, TxCRC).
NOTES:
*H = High byte – bits 15–8
L = Low byte – bits 7–0
Table 2.
FCS
Error Control
DESCRIPTION
Frame check sequence is transmitted/received
as 16 bits following the last data character of a
BOP message. The divisor is usually
CRC–CCITT (X
16
+ X
12
+ X
5
+ 1) with dividend
preset to 1’s but can be other wise determined
by ECM. The inverted remainder is transmitter as
the FCS.
Block check character is transmitted/received as
two successive characters following the last data
character of a BCP message. The polynomial is
CRC–16 (X
16
+ X
15
+ X
2
+ 1) or CRC–CCITT
with dividend preset to 0’s (as specified by
ECM). The true remainder is transmitted as the
BCC.
Table 3.
OPERATION
BOP
FLAG
ABORT
Special Characters
BIT PATTERN
01111110
11111111 generation
01111111 detection
FUNCTION
Frame message
Terminate communication
Terminate loop mode
repeater function
Secondary station address
CHARACTER
GA
Address
BCP
SYNC
01111111
(PCSAR
L
)
1
(PCSAR
L
) or
(TxDB)
2
generation
BCC
Character synchronization
NOTES:
1. ( ) = contents of.
2. For IDLE = 0 or 1 respectively.
11
IDLE
10
9
ECM
9
RxCL
9
8
RxDB
8
8
7
6
5
4
3
2 1
0
15
PCSAR
APA
15
PCR
15
RDSR
RERR
15
TDSR
TERR
14
14
PROTO
14
TxCL
14
13
13
SS/GA
13
12
SAM
S/AR
12
11
10
Tx
Rx
CL
CL
E
E
11
ROR
10
RAB/
GA
10
12
A B C
13
12
REOM RSOM
9
8
11
TGA
NOT DEFINED
TABORT TEOM TSOM
TxDB
NOTE:
Refer to Register Formats for mnemonics and description.
SD00059
Figure 3. Short Form Register Bit Formats
1995 May 01
5
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