INTEGRATED CIRCUITS
SCC2681
Dual asynchronous receiver/transmitter
(DUART)
Product data
2004 Apr 06
Philips
Semiconductors
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681
DESCRIPTION
The Philips Semiconductors SCC2681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. It interfaces directly with microprocessors and may be
used in a polled or interrupt driven system. It is manufactured in a
CMOS process.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16× clock derived from a programmable counter/timer,
or an external 1× or 16× clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the buffer of the receiving device is
full.
Also provided on the SCC2681 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
The SCC2681 is available in three package versions: 40-pin and
28-pin DIPs (both 0.6” wide); and a 44-pin PLCC.
•
16-bit programmable Counter/Timer
–
Non-standard rates to 115.2 kb
–
One user-defined rate derived from programmable
timer/counter
–
External 1× or 16× clock
•
Parity, framing, and overrun error detection
•
False start bit detection
•
Line break detection and generation
•
Programmable channel mode
–
Normal (full-duplex)
–
Automatic echo
–
Local loopback
–
Remote loopback
•
Multi-function programmable 16-bit counter/timer
•
Multi-function 7-bit input port
–
Can serve as clock or control inputs
–
Change of state detection on four inputs
–
100 kΩ typical pull-up resistor
•
Multi-function 8-bit output port
–
Individual bit set/reset capability
–
Outputs can be programmed to be status/interrupt signals
–
DMA signals
–
Auto 485 turn-around
•
Versatile interrupt system
–
Single interrupt output with eight maskable interrupting
conditions
–
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
FEATURES
•
Dual full-duplex asynchronous receiver/transmitter
•
Quadruple buffered receiver data registers
•
Programmable data format
–
5 to 8 data bits plus parity
–
Odd, even, no parity or force parity
–
1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•
Programmable baud rate for each receiver and transmitter
selectable from:
–
22 fixed rates: 50 to 115.2 k baud
•
Maximum data transfer: 1× – 1 MB/sec; 16× – 125 kB/sec
•
Automatic wake-up mode for multidrop applications
•
Start-end break interrupt/status
•
Detects break which originates in the middle of a character
•
On-chip crystal oscillator
•
Single +5 V power supply
•
Commercial and industrial temperature ranges available
•
DIP and PLCC packages
ORDERING INFORMATION
Type number
Package
Name
SCC2681AC1A44
SCC2681AC1N28
SCC2681AC1N40
PLCC44
DIP28
DIP40
Description
plastic leaded chip carrier; 44 leads
plastic dual in-line package; 28 leads (600 mil)
plastic dual in-line package; 40 leads (600 mil)
Version
SOT187-2
SOT117-1
SOT129-1
Commercial; V
CC
= +5 V
±
5%; T
amb
= 0
°C
to +70
°C
Industrial; V
CC
= +5 V
±
10%; T
amb
= –40
°C
to +85
°C
SCC2681AE1A44
SCC2681AE1N28
SCC2681AE1N40
2004 Apr 06
PLCC44
DIP28
DIP40
plastic leaded chip carrier; 44 leads
plastic dual in-line package; 28 leads (600 mil)
plastic dual in-line package; 40 leads (600 mil)
2
SOT187-2
SOT117-1
SOT129-1
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681
PIN CONFIGURATIONS
INDEX
CORNER
A0
IP3
A1
IP1
A2
A3
IP0
WRN
1
2
3
4
5
6
7
8
40 V
CC
39 IP4
38 IP5
37 IP6
36 IP2
35 CEN
34 RESET
33 X2
32 X1/CLK
31 RXDA
DIP
TXDB 11
OP1 12
OP3
13
30 TXDA
29 OP0
28 OP2
27 OP4
26 OP6
25 D0
24 D2
23 D4
22 D6
21 INTRN
A0
A1
A2
A3
WRN
RDN
RXDB
TXDB
OP1
D1
D3
1
2
3
4
5
6
7
DIP
8
9
10
11
21 TXDA
20 OP0
19 D0
18 D2
17 D4
16 D6
15 INTRN
28 V
CC
27 IP2
26 CEN
25 RESET
24 X2
23 X1/CLK
22 RXDA
17
18
TOP VIEW
PIN/FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A0
IP3
A1
IP1
A2
A3
IP0
WRN
RDN
RXDB
NC
TXDB
OP1
OP3
OP5
OP7
D1
D3
D5
D7
GND
PIN/FUNCTION
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
INTRN
D6
D4
D2
D0
OP6
OP4
OP2
OP0
TXDA
NC
RXDA
X1/CLK
X2
RESET
CEN
IP2
IP6
IP5
IP4
V
CC
28
29
PLCC
7
6
40
39
1
RDN 9
RXDB 10
OP5 14
OP7 15
D1 16
D3 17
D5 18
D7 19
GND 20
D5 12
D7
13
GND 14
SD00723
Figure 1. Pin configurations
PIN DESCRIPTION
SYMBOL
D0–D7
PIN
PLCC44
28, 18,
27, 19,
26, 20,
25, 21
39
DIP40
25, 16,
24, 17,
23, 18,
22, 19
35
DIP28
19, 10,
18, 11,
17, 12,
16, 13
26
TYPE
I/O
NAME AND FUNCTION
Data Bus:
Bidirectional 3-State data bus used to transfer commands, data and status
between the DUART and the CPU. D0 is the least significant bit.
CEN
I
Chip Enable:
Active-LOW input signal. When LOW, data transfers between the CPU
and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3
inputs. When HIGH, places the D0-D7 lines in the 3-State condition.
Write Strobe:
When LOW and CEN is also LOW, the contents of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of the signal.
Read Strobe:
When LOW and CEN is also LOW, causes the contents of the
addressed register to be presented on the data bus. The read cycle begins on the
falling edge of RDN.
Address Inputs:
Select the DUART internal registers and ports for read/write
operations.
Reset:
A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts
OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channels A and B in the
inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Clears Test
modes, sets MR pointer to MR1.
Interrupt Request:
Active-LOW, open-drain, output which signals the CPU that one or
more of the eight maskable interrupting conditions are true.
Crystal 1:
Crystal connection or an external clock input. A crystal of a clock the
appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal
connections see Figure 7, Clock Timing.
WRN
RDN
9
10
8
9
5
6
I
I
A0–A3
RESET
2, 4, 6, 7
38
1, 3, 5,
6
34
1–4
25
I
I
INTRN
X1/CLK
24
36
21
32
15
23
O
I
2004 Apr 06
3
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681
SYMBOL
X2
RxDA
RxDB
TxDA
PIN
PLCC44
37
35
11
33
DIP40
33
31
10
30
DIP28
24
22
7
21
TYPE
I
I
I
O
NAME AND FUNCTION
Crystal 2:
Crystal connection. See Figure 7. If a crystal is not used it is best to keep
this pin not connected although it
must not be
grounded.
Channel A Receiver Serial Data Input:
The least significant bit is received first. “Mark”
is HIGH, “space” is LOW.
Channel B Receive Serial Data Input:
The least significant bit is received first. “Mark”
is HIGH, “space” is LOW.
Channel A Transmitter Serial Data Output:
The least significant bit is transmitted
first. This output is held in the “mark” condition when the transmitter is disabled, idle or
when operating in local loopback mode. “Mark” is HIGH, “space” is LOW.
Channel B Transmitter Serial Data Output:
The least significant bit is transmitted
first. This output is held in the “mark” condition when the transmitter is disabled, idle or
when operating in local loopback mode. “Mark” is HIGH, “space” is LOW.
Output 0:
General purpose output or Channel A request to send (RTSAN,
active-LOW). Can be deactivated automatically on receive or transmit.
Output 1:
General purpose output or Channel B request to send (RTSBN,
active-LOW). Can be deactivated automatically on receive or transmit.
Output 2:
General purpose output or Channel A transmitter 1× or 16× clock output, or
Channel A receiver 1× clock output.
Output 3:
General purpose output or open-drain, active-LOW counter/timer interrupt
output or Channel B transmitter 1× clock output, or Channel B receiver 1× clock output.
Output 4:
General purpose output or Channel A open-drain, active-LOW,
RxRDYA/FFULLA interrupt output.
Output 5:
General purpose output or Channel B open-drain, active-LOW,
RxRDYB/FFULLB interrupt output.
Output 6:
General purpose output or Channel A open-drain, active-LOW, TxRDYA
interrupt output.
Output 7:
General purpose output or Channel B open-drain, active-LOW, TxRDYB
interrupt output.
Input 0:
General purpose input or Channel A clear to send active-LOW input (CTSAN).
Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 1:
General purpose input or Channel B clear to send active-LOW input (CTSBN).
Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 2:
General purpose input or counter/timer external clock input. Pin has an internal
V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 3:
General purpose input or Channel A transmitter external clock input (TxCA).
When the external clock is used by the transmitter, the transmitted data is clocked on
the falling edge of the clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 4:
General purpose input or Channel A receiver external clock input (RxCA).
When the external clock is used by the receiver, the received data is sampled on the
rising edge of the clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of
current.
Input 5:
General purpose input or Channel B transmitter external clock input (TxCB).
When the external clock is used by the transmitter, the transmitted data is clocked on
the falling edge of the clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 6:
General purpose input or Channel B receiver external clock input (RxCB).
When the external clock is used by the receiver, the received data is sampled on the
rising edge of the clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of
current.
Power Supply:
+5V supply input.
Ground
Not connected.
TxDB
13
11
8
O
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
IP3
32
14
31
15
30
16
29
17
8
5
40
3
29
12
28
13
27
14
26
15
7
4
36
2
20
9
–
–
–
–
–
–
–
–
27
–
O
O
O
O
O
O
O
O
I
I
I
I
IP4
43
39
–
I
IP5
42
38
–
I
IP6
41
37
–
I
V
CC
GND
n.c.
44
22
1, 12,
34, 23
40
20
–
28
14
–
I
I
–
2004 Apr 06
4
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
T
amb
T
stg
PARAMETER
Operating ambient temperature range
2
Storage temperature range
All voltages with respect to ground
3
Pin voltage range
RATING
See Note 4
–65 to +150
–0.5 to +6.0
V
SS
– 0.5 V to V
CC
+ 0.5 V
UNIT
°C
°C
V
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150
°C
maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
CC
supply range.
DC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= –40
°C
to +85
°C;
V
CC
= +5.0 V
±
10%
SYMBOL
V
IL
V
IH
V
IH
V
IH
V
OL
V
OH
I
IX1
I
ILX1
I
IHX1
I
OHX2
I
OHX2S
I
OLX2
I
OLX2S
I
I
I
OZH
I
OZL
I
ODL
I
ODH
I
CC
PARAMETER
LOW-level input voltage
HIGH-level input voltage (except X1/CLK)
HIGH-level input voltage (except X1/CLK)
HIGH-level input voltage (X1/CLK)
LOW-level output voltage
HIGH-level output voltage (except open-drain outputs)
4
X1/CLK input current
X1/CLK input LOW current – operating
X1/CLK input HIGH current – operating
X2 output HIGH current – operating
X2 output HIGH short circuit current – operating
X2 output LOW current – operating
X2 output LOW short circuit current – operating
Input leakage current:
All except input port pins
Input port pins
Output off current HIGH, 3-state data bus
Output off current LOW, 3-state data bus
Open-drain output LOW current in off-state
Open-drain output HIGH current in off-state
Power supply current
5
Operating mode
TEST CONDITIONS
T
amb
≥
0
°C
T
amb
< 0
°C
I
OL
= 2.4 mA
I
OH
= –400
µA
V
IN
= 0 V to V
CC
V
IN
= 0 V
V
IN
= V
CC
V
OUT
= V
CC
; X1 = 0
V
OUT
= 0 V; X1 = 0
V
OUT
= 0 V; X1 = V
CC
V
OUT
= V
CC
; X1 = V
CC
V
IN
= 0 V to V
CC
V
IN
= 0 V to V
CC
V
IN
= V
CC
V
IN
= 0 V
V
IN
= 0 V
V
IN
= V
CC
CMOS input levels
LIMITS
Min
–
2.0
2.5
0.8 V
CC
–
V
CC
– 0.5
–10
–75
0
0
–10
–75
1
–10
–20
–
–10
–10
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
0.8
–
–
–
0.4
–
+10
0
75
+75
–1
0
10
+10
+10
10
–
–
10
10
UNIT
V
V
V
V
V
V
µA
µA
µA
µA
mA
µA
mA
µA
µA
µA
µA
µA
µA
mA
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
3. Typical values are at +25
°C,
typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C
L
= 150 pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 50 pF, R
L
= 2.7 kΩ to V
CC
.
5. All outputs are disconnected. Inputs are switching between CMOS levels of V
CC
– 0.2 V and V
SS
+ 0.2 V.
2004 Apr 06
5
京公网安备 11010802033920号
EEWORLD
