Advanc Pow
A
ced
wer
Electron
E
nics Co
orp.
APE8837
DUAL CHAN
NNEL L
LDO RE
EGULAT
TORS W
WITH ENABLE
E
FEATUR
RES
▓
▓
▓
DES
SCRIPTIO
ON
The APE8837 is a high accu
A
urately, low noise, high
n
ripple rejection ra
e
atio, low drop
pout, dual CMOS LDO
voltag regulator with enab function. The EN
ge
rs
ble
function allows th output of each regulator to be
he
f
turned off indepen
d
ndently, resulting in great reduced
tly
power consumptio
on.
The APE8837 has the soft sta function to suppress
A
s
art
o
the in
nrush current. The current limit is ov 250mA
ver
per ch
hannel and a
also operates as a short protection
for the output cur
rrent limiter. The output voltage for
v
each regulator is set inde
ependently by metal
trimm
ming.
The APE8837 is fully comp
s
patible with low ESR
ceram capacito
mic
ors, reducing cost and improving
g
outpu stability. T
ut
This high le
evel output stability is
maint
tained even during frequ
uent load flu
uctuations,
and high PSRR a
h
achieved across a broad range of
d
freque
ency. It is a
available in t
the SOT-26, TSOT-26
,
and DFN 2x2 pac
D
ckages.
Input Volt
tage Range : 2.5V to 6V
Varied Fix Output V
xed
Voltage Com
mbinations
200mV D
Dropout at 20
00mA Output Current (Vout
≧2.5V)
Output Current: 200m
mA/channel (typ.)
Low Quie
escent Curre : 60uA (ty
ent
yp.)
Current L
Limit and Sho Current P
ort
Protection
Thermal Shutdown Protection
Fast Tran
nsient Respo
onse
Low ESR Capacitor C
R
Compatible (X
X7R, X5R)
Halogen Free Produc
ct
▓
▓
▓
▓
▓
▓
▓
.
due to the excelle transient response pe
o
ent
erformance
TYPICA APPLICATION
AL
VIN
CIN
2.2uF
VO
OUT2
EN 2
VIN
EN
E 1
VOUT
T1
VOU T 2
VOU 1
UT
GND
COUT2
2.2uF
8837
APE8
COUT1
2.2uF
ecifications su
ubject to chang without not
ge
tice
Data and spe
1
20140331V7.4
4
Advanc Pow
A
ced
wer
Electron
E
nics Co
orp.
ORDERING / PA
ACKAGE INFORM
MATION
APE8837 X
XX
Packa Type
age
Y: SOT
T-26
TY: TS
SOT-26
GN2: DFN 2x2-6L
D
Output Type Code
t
1
EN1
APE8837
Top View
w
SOT-26 / TSO
OT-26
VOUT1 GND V
VOUT2
6
5
4
(Marking)
2
VIN
3
EN2
Ou
utput Type C
Code : (V
OUT
+V
OUT2
)
T1
A : 1.5V+
+2.8V
B : 1.8V+
+2.8V
C : 1.8V+
+2.6V
D : 1.8V+
+3.3V
E : 2.5V+
+2.8V
F : 2.8V+
+1.2V
G : 2.8V+
+1.8V
H : 2.8+3
3.0V
J: 2
2.8+3.3V
K : 3.0+3.0V
L : 3.
.0V+3.3V
M:3
3.3V+3.3V
N : 1.2V+3.3V
P : 1.8V+3.0V
Q : 1.5V+2.5V
R : 3.3V+1.8V
S:
S 1.2V+1.8V
V
T : 1.5V+3.3V
V
U : 2.5V+2.5
5V
V : 1.5V+3.0
0V
W : 1.2V+2.8
8V
X : 1.2V+1.2V
V
Y : 2.8V+1.5
5V
Z : 2.8V+2.8V
V
EN
N1
VI
N
Top View
w
DFN 2x2-6
6L
1
2
Exposed
Pad
6
VOUT1
5
GND
4
VOUT2
EN
3
N2
GND
.
ABSOLU
UTE MAX
XIMUM R
RATINGS
(at T
A
=25°C
S
C)
VIN
VOUT1, VO
OUT2
EN1, EN2
Output Current (I
O1
+I
O2
)
Junction Te
emperature (T
J
)
Operating T
Temperature Range (T
OP
)
e
P
Storage Temperature R
Range (T
ST
)
Lead Temp
perature (Soldering, 10se
ec.)
Thermal Re
esistance from Junction t Ambient (R
JA
)
to
Rθ
SOT-26 / T
TSOT-26
DFN 2x2-6L
N
Thermal R
Resistance f
from Junctio to Case (Rθ
JC
)
on
SOT-26 / T
TSOT-26
DFN 2x2-6L
N
180C
C/W
25°C
C/W
2
-0.3V to 6.5V
V
-0.3V to 6.5V
V
-0.3V to 6.5V
V
800m
mA
-40 to 125°C
t
-40°C to 85°C
-65 to +150°C
t
260°
°C
250°
°C/W
120°
°C/W
Note: Rθ
JA
is m
measured with t PCB coppe area of appro
the
er
oximately 1 in (M
Multi-layer) whic connect to G
ch
GND pin or exposed pad (DFN
N
2x2-6L).
2
Advanc Pow
A
ced
wer
Electron
E
nics Co
orp.
ELECTR
RICAL SP
PECIFICA
ATIONS
(V
IN
=5V, T
A
=25°C, unless otherwise specified)
e
RAMETER
PAR
Input Voltag
ge
Output Volta Accuracy
age
y
Quiescent C
Current
SY
YM
V
IN
∆V
OUT
V
I
C
CC
TEST CON
NDITION
I
OUT
=10mA
1mA, V
IN
=5V V
OUT
>1.8V
V,
V
I
OUT
=1
I
OUT
=1
1mA, V
IN
=5V
OUT
≦1.8V
V,V
V
I
OUT1,2
=
=0mA, V
IN
=5
5V
I
OUT
=0
0.2A, V
O
=V
O
-2%, V
OUT
=1.
-
.2V
Dropout Vol
ltage
V
DROP
I
OUT
=0
0.2A, V
O
=V
O
-2%, V
OUT
=1.
-
.5V
I
OUT
=0
0.2A, V
O
=V
O
-2%, V
OUT
=1.
-
.8V
I
OUT
=0
0.2A, V
O
=V
O
-2%, V
OUT
>2.
-
.5V
Current Lim
(Note1)
mit
Short Circui Current
it
Line Regula
ation
Load Regulation
(Note 1)
Ripple Rejection
(Note2)
Output Volta Tempera
age
ature
(Note2)
Coefficient
(
APE8837
MIN
2.5
-2
-0.04
TYP
MA
AX
6
2
0.
.04
UNIT
V
%
V
uA
mV
mV
mV
mV
mA
60
1100
800
500
200
250
150
0.2
0.01
60
+100
1.7
1.4
100
15
500
12
200
900
400
I
LIMIT
I
S
SC
∆V
LINE
V
∆V
L
LOAD
PS
SRR
T.C.
V
IN
=V
O
+1.0V, V
EN
=V
IN
OUT
E
ut
0
Outpu Voltage < 0.25xV
OUT
,
each c
channel
I
OUT
=1
1mA, V
IN
=V
OUT
+1V to 6.0
0V
O
I
OUT
=1
1~100mA, V
IN
=V
OUT
+1V
f=120H I
OUT
= 30m
Hz,
.
mA
I
OUT
=1mA
V
IN
=5V
V
V
IN
=3.
.3V
V
IN
=5V
V
V
IN
=3.
.3V
V
EN1,2
= 0V
I
OUT1,2
=0mA, V
IN
=5 V
EN1,2
=0V
5V,
V
mA
0.3
0
0.
.03
%/V
%/mA
dB
ppm/
ºC
V
V
1.2
1.0
V
V
uA
uA
o
o
V
E
ENH
Enable Inpu Threshold
ut
V
E
ENL
Enable Pull-
-high Curren
nt
Shutdown C
Current
Thermal Shutdown Thre
eshold
(Note2)
I
EN
N1,2
I
S
SD
T
SD
-
-
1
2
150
2
4
C
C
Hyster
resis
40
Note1: It is measured at constant jun
t
nction tempe
erature by us
sing pulsed te
esting with a low ON time
e.
Note2: Guarantee by de
esign, not pro
oduction test
ted.
3
Embedded System
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