HCSL/ LVCMOS Clock Generator
8413S12
DATA SHEET
General Description
The 8413S12 is a PLL-based clock generator. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express, sRIO, XAUI, SerDes reference
clocks and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs.
The output frequencies are generated from a 25MHz external input
source or an external 25MHz parallel resonant crystal. The industrial
temperature range of the 8413S12 supports telecommunication,
networking, and storage requirements.
Features
•
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Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for PCI Express, sRIO and GbE, HCSL interface levels
One single-ended QG LVCMOS/LVTTL clock output at 125MHz
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15 output impedance
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15 output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
Applications
•
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CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
•
Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
Pin Assignment
V
DDO_QREF
OE_REF
QREF1
QREF0
V
DDO_G
V
DDO_E
V
DDO_F
OE_G
OE_E
nQE1
nQE0
•
•
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
nMR
QE1
QE0
QG
QF
nc
nc
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
GND
FSEL_A0
FSEL_A1
FSEL_B0
FSEL_B1
FSEL_C0
FSEL_C1
FSEL_D0
FSEL_D1
FSEL_E0
V
DDA
FSEL_E1
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
nc
V
DD
IREF
OE_D
nQD1
QD1
nQD0
QD0
V
DDO_D
V
DDO_C
nQC1
QC1
nQC0
QC0
OE_C
V
DD
GND
nc
nc
PLL_SEL
CLK
V
DD
nCLK
OE_A
QA0
nQA0
QA1
nQA1
OE_B
QB0
V
DDO_A
nQB0
QB1
nQB1
REVISION D 1/27/15
V
DDO_B
nc
1
©2015 INTEGRATED DEVICE TECHNOLOGY, INC.
8413S12 DATA SHEET
Block Diagram
nMR
Pullup
OE_A
2
2
2
2
2
Clock
Output
Control
Logic
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
QA0,
nQA0
QA1,
nQA1
OE_B
QB0,
nQB0
QB1,
nQB1
OE_C
QC0,
nQC0
QC1,
nQC1
OE_D
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
QD0,
nQD0
QD1,
nQD1
OE_E
QE0,
nQE0
QE1,
nQE1
FSEL_A [0:1]
FSEL_B [0:1]
FSEL_C [0:1]
FSEL_D [0:1]
FSEL_E [0:1]
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
PLL_SEL
REF_SEL
Pullup
Pullup
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
CLK,
nCLK
Pulldown
0
Pullup/
Pulldown
0
1
OSC
VCO
1
XTAL_IN
XTAL_OUT
IREF
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
50MHz
QF
OE_G
125MHz
QG
OE_REF
QREF0
QREF1
NOTE:
OE_[A:G] and OE_REF pins have pullup resistors.
HCSL/ LVCMOS CLOCK GENERATOR
2
REVISION D 1/27/15
8413S12 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 18, 38
2,
3
4,
5
6,
7
8,
9
10,
12
11
13, 16, 19,
36, 37, 54,
55, 72
14,
15
17
20, 39, 53
21
22
23
24
25
26, 27
28, 29
30
31, 32
33, 34
35
40
41, 42
43, 44
45
46
47, 48
49, 50
Name
GND
FSEL_A0.
FSEL_A1
FSEL_B0,
FSEL_B1
FSEL_C0,
FSEL_C1
FSEL_D0,
FSEL_D1
FSEL_E0,
FSEL_E1
V
DDA
nc
XTAL_IN,
XTAL_OUT
REF_SEL
V
DD
PLL_SEL
CLK
nCLK
OE_A
V
DDO_A
QA0, nQA0
QA1, nQA1
OE_B
QB0, nQB0
QB1, nQB1
V
DDO_B
OE_C
QC0, nQC0
QC1, nQC1
V
DDO_C
V
DDO_D
QD0, nQD0
QD1, nQD1
Power
Input
Input
Input
Input
Input
Power
Unused
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Type
Description
Power supply ground.
Selects the QAx, nQAx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QBx, nQBx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QCx, nQCx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QDx, nQDx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QEx, nQEx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Analog supply pin.
No connect.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
Pullup
Input source control pin. See Table 3C. LVCMOS/LVTTL interface levels.
Core supply pins.
Pullup
Pulldown
Pullup/
Pulldown
Pullup
PLL bypass control pin. See Table 3B. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Active HIGH output enable for Bank A outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Bank A (HCSL) output supply pin. 3.3 V supply.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Pullup
Active HIGH output enable for Bank B outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank B (HCSL) output supply pin. 3.3V supply.
Pullup
Active HIGH output enable for Bank C outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank C (HCSL) output supply pin. 3.3V supply.
Bank D (HCSL) output and HCSL reference circuit supply pin. Must be
connected to 3.3V to use any of the HCSL outputs.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Input
Input
Power
Input
Input
Input
Input
Power
Output
Output
Input
Output
Output
Power
Input
Output
Output
Power
Power
Output
Output
REVISION D 1/27/15
3
HCSL/ LVCMOS CLOCK GENERATOR
8413S12 DATA SHEET
Table 1. Pin Descriptions (Continued)
Number
51
Name
OE_D
Input
Type
Pullup
Description
Active HIGH output enable for Bank D outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
External fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode Q[Ax:Ex], nQ[Ax:EX]
outputs.
Bank E (HCSL) output supply pin. 3.3V supply.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Pullup
Active HIGH output enable for Bank E outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Active LOW Master Reset. When logic LOW, all outputs are reset causing
the true outputs Qx to go low and the inverted outputs nQx to go high. When
logic HIGH, all outputs are enabled. LVCMOS/LVTTL interface levels.
QF output supply pin (LVCMOS/LVTTL). 3.3V supply.
Single-ended output. 3.3V LVCMOS/LVTTL interface levels.
QG output supply pins (LVCMOS/LVTTL). 3.3V or 2.5V supply.
Single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
Pullup
Pullup
Active HIGH output enable for Bank G output. See Table 3E.
LVCMOS/LVTTL interface levels.
Active HIGH output enable for QREF[0:1] outputs. See Table 3F.
LVCMOS/LVTTL interface levels.
Single-ended REF outputs. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
QREF[0:1] output supply pin (LVCMOS/LVTTL). 3.3V or 2.5V supply.
52
56
57, 58
59, 60
61
I
REF
V
DDO_E
QE0, nQE0
QE1, nQE1
OE_E
Input
Power
Output
Output
Input
62
63
64
65
66
67
68
69,
70
71
nMR
V
DDO_F
QF
V
DDO_G
QG
OE_G
OE_REF
QREF0,
QREF1
V
DDO_QREF
Input
Power
Output
Power
Output
Input
Input
Output
Power
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output
Impedance
QF, QG,
QREF[0:1]
QG,
QREF[0:1]
V
DDO_F
= V
DDO_G
= V
DDO_QREF
=
3.465V
V
DDO_QREF
, V
DDO_G
= 2.625V
Test Conditions
Minimum
Typical
2
51
51
15
15
Maximum
Units
pF
k
k
R
OUT
HCSL/ LVCMOS CLOCK GENERATOR
4
REVISION D 1/27/15
8413S12 DATA SHEET
Function Tables
Table 3A. FSEL_X Control Input Function Table
Input
FSEL_X[0:1]
00 (default)
01
10
11
Output Frequency
Q[Ax:Ex], nQ[Ax:Ex]
100MHz
125MHz
156.25MHz
312.50MHz
Table 3D. OE_[A:E] Control Input Function Table
Input
OE_[A:E]
0
1 (default)
Outputs
Q[Ax:Ex], nQ[Ax:Ex]
High-Impedance
Enabled
NOTE: FSEL_X denotes FSEL_A, _B, _C, _D, _E.
NOTE Any two outputs operated at the same frequency will be
synchronous.
Table 3E. OE_G Control Input Function Table
Input
OE_G
0
1 (default)
Outputs
QG
High-Impedance
Enabled
Table 3B. PLL_SEL Control Input Function Table
Input
PLL_SEL
0
1 (default)
Operation
PLL Bypass
PLL Mode
Table 3F. OE_REF Control Input Function Table
Input
OE_REF
Output
QREF[0:1]
High-Impedance
Enabled
Table 3C. REF_SEL Control Input Function Table
Input
REF_SEL
0
1 (default)
Clock Source
CLK, nCLK
XTAL_IN, XTAL_OUT
0
1 (default)
REVISION D 1/27/15
5
HCSL/ LVCMOS CLOCK GENERATOR
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