K9K8G08U1M
K9F4G08U0M
Advance
FLASH MEMORY
Document Title
512M x 8 Bits / 1G x 8 Bits NAND Flash Memory
Revision History
Revision No
0.0
History
1. Initial issue
Draft Date
Nov. 15. 2004
Remark
Advance
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
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K9K8G08U1M
K9F4G08U0M
Advance
FLASH MEMORY
512M x 8 Bit / 1G x 8 Bits NAND Flash Memory
PRODUCT LIST
Part Number
K9F4G08U0M-Y,P
K9F4G08U0M-I
K9K8G08U1M-I
2.70 ~ 3.60V
X8
Vcc Range
Organization
PKG Type
TSOP1
52ULGA
FEATURES
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Voltage Supply
- 2.70V ~ 3.60V
•
Organization
- Memory Cell Array : (512M + 16,384K)bit x 8bit
- Data Register : (2K + 64)bit x 8bit
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Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (128K + 4K)Byte
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Page Read Operation
- Page Size : (2K + 64)Byte
- Random Read : 20µs(Max.)
- Serial Access : 25ns(Min.)
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Fast Write Cycle Time
- Page Program time : 200µs(Typ.)
- Block Erase Time : 1.5ms(Typ.)
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Command/Address/Data Multiplexed I/O Port
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Hardware Data Protection
- Program/Erase Lockout During Power Transitions
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Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
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Command Driven Operation
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Intelligent Copy-Back with internal 1bit/528Byte EDC
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Unique ID for Copyright Protection
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Package :
- K9F4G08U0M-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F4G08U0M-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F4G08U0M-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.00 mm pitch)
- K9K8G08U1M-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.00 mm pitch)
GENERAL DESCRIPTION
Offered in 512Mx8bit, the K9F4G08U0M is a 4G-bit NAND Flash Memory with spare 128M-bit. Its NAND cell provides the most cost-
effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte
page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data page can be read out at
25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip
write controller automates all program and erase functions including pulse repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take advantage of the K9F4G08U0M′s extended reliability of 100K program/
erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F4G08U0M is an optimum solu-
tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
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