9ZX21200 datasheet, PDF - EEWORLD Datasheet

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9ZX21200: DescriptionSpace-saving 56-pin package; File Size211KB，17 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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9ZX21200 Overview

Space-saving 56-pin package

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DATASHEET

12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI

9ZX21200

Description

The 9ZX21200 is a small-footprint 12-output differential

buffer that meets all the performance requirements of the

Intel DB1200Z specification. The 9ZX21200 is backwards

compatible to PCIe Gen1 and Gen2 applications. A fixed,

internal feedback path maintains low drift for critical QPI

applications. In bypass mode, the 9ZX21200 can provide

outputs up to 150MHz.

Features/Benefits

•

Space-saving 56-pin package

•

Fixed feedback path for 0ps input-to-output delay

•

9 Selectable SMBus Addresses; Mulitple devices can

share the same SMBus Segment

Recommended Application

12-output PCIe Gen3/ QPI differential buffer for Romley and

newer platforms

•

4 OE# pins; Hardware control of four outputs

•

PLL or bypass mode; PLL can dejitter incoming clock

•

100MHz or 133MHz PLL mode operation; supports PCIe

and QPI applications

•

Selectable PLL bandwidth; minimizes jitter peaking in

downstream PLL's

Key Specifications

•

Cycle-to-cycle jitter <50ps

Output-to-output skew < 65 ps

Input-to-output delay variation <50ps

PCIe Gen3 phase jitter < 1.0ps RMS

QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS

•

Spread Spectrum Compatible; tracks spreading input

clock for low EMI

•

Software control of PLL Bandwidth and Bypass

Settings/PLL can dejitter incoming clock (B Rev only)

Output Features

•

12 - 0.7V differential HCSL output pairs

Block Diagram

OE(8,6,4,2)#

DFB_OUT

Z-PLL

(SS Compatible)

DIF(11:0)

DIF_IN

DIF_IN#

HIBW_BYPM_LOBW#

100M_133M#

CKPWRGD/PD#

SMB_A0_tri

SMB_A1_tri

SMBDAT

SMBCLK

Logic

IREF

IDT®

12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI

9ZX21200

REV D 041513

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