ECS-330-20-33Q-JDM-TR datasheet, PDF

Datasheet> All Categories > Passive components> Crystal/resonator> ECS-330-20-33Q-JDM-TR

ECS-330-20-33Q-JDM-TR: DescriptionParallel - Fundamental Quartz Crystal,; CategoryPassive components Crystal/resonator; File Size421KB，2 Pages; ManufacturerECS; Websitehttp://www.ecsxtal.com/; Environmental Compliance

Download Datasheet Parametric View All

ECS-330-20-33Q-JDM-TR Overview

Parallel - Fundamental Quartz Crystal,

ECS-330-20-33Q-JDM-TR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	7180196549
package instruction	SMD, 4 PIN
Reach Compliance Code	compliant
Other features	AEC-Q200
Ageing	5 PPM/FIRST YEAR
Crystal/Resonator Type	PARALLEL - FUNDAMENTAL
Drive level	100 µW
frequency stability	0.01%
frequency tolerance	20 ppm
JESD-609 code	e4
load capacitance	20 pF
Installation features	SURFACE MOUNT
Nominal operating frequency	33 MHz
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
physical size	3.2mm X 2.5mm X 0.8mm
Series resistance	40 Ω
surface mount	YES
Terminal surface	Gold (Au) - with Nickel (Ni) barrier

Preview

Download Datasheet

View All

ECX-33Q

SMD CRYSTAL

The ECX-33Q is a miniature SMD Crystal with a 3.2 x 2.5 mm

footprint. AEC-Q200 Qualified.

Request a Sample

ECX-33Q SMD CRYSTAL

OPERATING CONDITIONS / ELECTRICAL CHARACTERISTICS

PARAMETERS

Frequency

Mode of Oscillation

Frequency Tolerance*

Frequency Stability*

Shunt Capacitance

Fundamental

@ +25°C

-55 ~ +125°C

(DU Option)

CONDITIONS

MIN

ECX-33Q

TYP

MAX

UNITS

54.000

± 30

± 100

MHz

ppm

μW

°C

ppm

ESR Ω Max.

500

100

8.000

Specify in P/N

opr

(DU Option)

•

Low Profile

3.2 x 2.5 mm Footprint

RoHS Compliant

AEC-Q200 Qualified

Load Capacitance

Drive Level

Operating Temperature*

Storage Temperature

Aging (First Year)

Series

100

-55

+125

±5

DIMENSIONS (mm)

stg

@ +25°C ±3°C

Frequency (MHz)

8.000 ~ 9.999

10.000 ~ 15.999

16.000 ~ 19.999

20.000 ~ 23.999

24.000 ~ 54.000

Figure 1)

Top, Side, and Bottom

Crystal is symmetrical, pad 1 & 3 are interchangeable.

Chamfer on the bottom pad has no electrical

significance.

Pad Connections

In/Out

Gnd

Out/In

Gnd

Figure 2)

Suggested land

pattern

PACKAGING

PART NUMBERING GUIDE: Example ECS-200-20-33Q-DU-TR

ECS - FREQUENCY ABBREVIATION

LOAD

CAPACITANCE

20 = 20 pF

10 = 10 pF

S = Series

PACKAGE

Tolerance

33Q =

ECX-33Q

Blank = ±30

ppm

A = ± 25

ppm

J = ± 20

ppm

R = ± 15

ppm

C = ± 10

ppm

AVAILABLE OPTIONS

Stability

D= ±100 ppm

E = ± 50 ppm

G = ± 30 ppm

H = ± 25 ppm

T = ± 20 ppm

†

W = ±15 ppm

†

K = ± 10 ppm

†

Temp Range

L = -10 ~ +70°C

M = -20 ~ +70°C

Y = -30 ~ +85°C

N = -40 ~ +85°C

P = -40 ~ +105°C

S = -40 ~ +125°C

U = -55 ~ +125°C

TR =

Tape

& Reel

ECS

200 = 20.000 MHz

See P/N Guide

* Specify available options in P/N.

†

Contact ECS for availability over extended temp range.

Rev.2021

15351 West 109

Street

Lenexa, KS 66219

Phone: 913.782.7787

Fax: 913.782.6991

www.ecsxtal.com

Recommended Resources

Circuit diagram of disconnection alarm composed of 555

RTS951 (9 tone) circuit

Eight-level touch volume controller circuit diagram composed of 74L194

Coin heads and tails indicator

AC and DC dual-use darkroom safety circuits

Low voltage, low power consumption, programmable crystal oscillator circuit

Xilinx acquires Auviz Systems, the battle between FPGA and GPU is finally about to begin: [url=http://www.leiphone.com/news/201609/S5tIHYiVfuXepluM.html]Original address[/url] Today, Xilinx announced the acquisition of Auviz Systems, shocking the artificial intelligence community. Auviz Sy...; 白丁 FPGA/CPLD

Design and implementation of signal acquisition based on DSP and FPGA: Design block diagram and implementation code of signal acquisition based on DSP and FPGA...; jiakun260 DSP and ARM Processors

MPLAB compile problem: Clean: Deleting intermediary and output files. Clean: Deleted file "C:\Program Files\Microchip\lzz1\lzz001.cce". Clean: Done. Executing: "C:\HT-PIC\BIN\PICC.EXE" -C -E"lzz001.cce" "lzz001.c" -O"lzz001...; youliam Embedded System

Regarding the nios burning problem, please help: I used ep2s180f1020i4 chip, configured chip epcs64, and used flash programmer to burn. From the status bar, it can be seen that the burning is successful, but there is no response after power on. Not ...; xixiangnan FPGA/CPLD

About am335x dual network port problem: Hello everyone: I use am3352 to connect two phys of different models (RTL8201 and IP101G). The phy physical addresses are 0 and 3, corresponding to network port 0 and network port 1 respectively, and ...; wangtongsheng DSP and ARM Processors

To make a simple PDA for around 200 yuan, which ARM should I choose?: I am planning to make a simple PDA with some basic functions, such as notepad, schedule, electronic dictionary, etc. It uses a small LCD display and touch screen input. I hope it has low power consump...; lfjwfm ARM Technology

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components