Ordering number : ENA1828
ENA1951
LC87F0808A
CMOS IC
8K-byte FROM and 256-byte RAM integrated
8-bit 1-chip Microcontroller
Overview
http://onsemi.com
The LC87F0808A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
50.0ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (On-board-
programmable), 256-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit
timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit timers with
a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface,
an asynchronous/synchronous SIO interface, a UART interface (full duplex), motor control PWM , a 10/8-bit 10-
channel AD converter, a system clock frequency divider, an internal reset and a 21-source 10-vector interrupt feature.
This microcomputer is suitable for small motor control equipment.
Features
Flash
ROM
•
Capable of On-board-programming with wide range (3.3 to 5.5V) of voltage source.
•
Block-erasable in 128 byte units
•
Writable in 2-byte units
•
8192
×
8 bits
RAM
•
256
×
9 bits
Minimum
Bus Cycle
•
50.0ns (20MHz at VDD=3.3V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.00
91510HKIM 20100823-S00001 No.A1828-1/25
LC87F0808A
Ports
•
Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1-bit units
Ports I/O direction can be designated in 4-bit units
•
Dedicated oscillator ports/input ports
•
Reset pin
•
On-chip Debugger pin
•
Power pins
20 (P1n, P20, P21, P30 to P35, P70 to P73)
8 (P0n)
2 (CF1/XT1, CF2/XT2)
1 (RES)
1 (OWP0)
4 (VSS1, VSS2, VDD1, VDD2)
Timers
•
Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
×
2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM)
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts are programmable in 5 different time schemes
3) The base timer is unavailable when the CF oscillator circuit is selected
SIO
•
SIO0: 8-bit Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART
•
Full Duplex
•
7/8/9 bit data bits selectable
• 1
Stop bit (2 bits in continuous data transmission)
•
Built-in baudrate generator
AD
Converter: 10 bits/8 bits
×
10 channels (internal: 2 channels)
•
10/8 bits AD converter resolution selectable
•
Auto start function (It links an interrupt factor of MCPWM)
No.A1828-2/25
LC87F0808A
Remote
Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
•
Noise rejection function (noise filter time constant selectable from 1 tCYC/32 tCYC/128 tCYC)
Clock
Output Function
•
Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as
the system clock.
•
Can generate the source clock for the subclock
Analog
Comparator / Amplifier
×
2 channels
•
Analog comparator / amplifier selectable (each channel)
•
Analog comparator Interrupt
MCPWM:
Motor Control 12-bit PWM
×
6 channels
•
Dead time is programmable.
•
Forced stop is possible by the output of the analog comparator and the INT terminals.
•
Edge-aligned / center-aligned selectable
Watchdog
Timer
•
Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed
RC oscillation clock (30kHz).
•
Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/HOLD mode.
Interrupts
•
21 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/Base timer
T0H
T1L/T1H
SIO0/UART1 receive
SIO1/UART1 transmit/MCPWM
ADC/T6/T7
Port 0/CMP1/CMP2
Interrupt Source
•
Priority levels X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine
Stack Levels: 128levels (The stack is allocated in RAM.)
High-speed
Multiplication/Division Instructions
•
16 bits
×
8 bits
(5 tCYC execution time)
•
24 bits
×
16 bits
(12 tCYC execution time)
•
16 bits
÷
8 bits
(8 tCYC execution time)
•
24 bits
÷
16 bits
(12 tCYC execution time)
No.A1828-3/25
LC87F0808A
Oscillation
Circuits
•
Internal oscillation circuits
Medium-speed RC oscillation circuit: For system clock (1MHz)
High-speed RC oscillation circuit:
For system clock (20MHz)
Low-speed RC oscillation circuit:
For watch dog timer (30kHz)
•
External oscillation circuits
Hi-speed CF oscillation circuit:
For system clock, with internal Rf
Low speed crystal oscillation circuit:
For low-speed system clock, with internal Rf
1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control.
2) The CF and the crystal oscillation circuits stop operating in the system reset state and start oscillating when the
oscillation is enabled with an instruction.
System
Clock Divider Function
•
Can run on low current.
•
The minimum instruction cycle selectable from 150ns, 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs and
38.4μs (at a main clock rate of 20MHz).
Internal
Reset Function
•
Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V and
4.35V) through option configuration.
•
Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, 4.28V).
Standby
Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by watchdog timer or low-voltage detection
(3) Having an interrupt source established at either INT0, INT1, INT2 or INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillator automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer or low-voltage detection.
(3) Having an interrupt source established at either INT0, INT1, INT2 or INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
Note: Available only when X’tal oscillation is selected.
No.A1828-4/25
LC87F0808A
On-chip
Debugger
•
Supports software debugging with the IC mounted on the target board.
Data
Security Function (flash versions only)
•
Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
Package
Form
•
QFP36 (7×7): Lead-/Halogen-free type
Development
Tools
•
On-chip debugger: TCB87 type C + LC87F0808A
Programming
Boards
Package
QFP36(7×7)
Programming boards
W87F24Q
Flash
ROM Programmer
Maker
Single
Programmer
Flash Support Group, Inc.
(FSG)
Gang
Programmer
Single/Gang
Programmer
Gang
Our company
Programmer
In-circuit/Gang
Programmer
Model
AF9709/AF9709B/AF9709C
(Including Ando Electric Co., Ltd. models)
AF9723/AF9723B(Main body)
(Including Ando Electric Co., Ltd. models)
AF9833(Unit)
(Including Ando Electric Co., Ltd. models)
SKK/SKK Type B
(SanyoFWS)
SKK-4G
(SanyoFWS)
SKK-DBG Type C
(SanyoFWS)
Supported Version
Rev 03.28 or later
-
-
Application Version
1.06 or later
Chip Data Version
2.26 or later
Application Version
1.06 or later
Chip Data Version
2.31 or later
LC87F0808
Device
87f008SU
(3B247)
-
-
For information about AF-Series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: sales@j-fsg.co.jp
No.A1828-5/25
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