INTEGRATED CIRCUITS
DATA SHEET
SAF7113H
9-bit video input processor
Product specification
File under Integrated Circuits, IC22
2000 May 08
Philips Semiconductors
Product specification
9-bit video input processor
CONTENTS
1
2
3
4
5
6
7
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
9
9.1
9.2
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Analog input processing
Analog control circuits
Chrominance processing
Luminance processing
Synchronization
Clock generation circuit
Power-on reset and CE input
Multi-standard VBI data slicer
VBI-raw data bypass
Digital output port VPO7 to VPO0
RTCO output
RTS0, RTS1 terminals
BOUNDARY SCAN TEST
Initialization of boundary scan circuit
Device identification codes
10
11
12
13
13.1
14
15
15.1
15.2
16
17
18
18.1
18.2
18.3
18.4
18.5
19
20
21
22
LIMITING VALUES
SAF7113H
THERMAL CHARACTERISTICS
CHARACTERISTICS
TIMING DIAGRAMS
Errata information
APPLICATION INFORMATION
I
2
C-BUS DESCRIPTION
I
2
C-bus format
I
2
C-bus detail
I
2
C-BUS START SET-UP
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2000 May 08
2
Philips Semiconductors
Product specification
9-bit video input processor
1
FEATURES
SAF7113H
•
Four analog inputs, internal analog source selectors,
e.g. 4
×
CVBS or 2
×
Y/C or (1
×
Y/C and 2
×
CVBS)
•
Two analog preprocessing channels in differential
CMOS style for best S/N-performance
•
Fully programmable static gain or automatic gain control
for the selected CVBS or Y/C channel
•
Switchable white peak control
•
Two built-in analog anti-aliasing filters
•
Two 9-bit video CMOS Analog-to-Digital Converters
(ADCs), digitized CVBS or Y/C-signals are available on
the VPO-port via I
2
C-bus control
•
On-chip clock generator
•
Line-locked system clock frequencies
•
Digital PLL for horizontal sync processing and clock
generation, horizontal and vertical sync detection
•
Requires only one crystal (24.576 MHz) for all standards
•
Automatic detection of 50 and 60 Hz field frequency,
and automatic switching between PAL and NTSC
standards
•
Luminance and chrominance signal processing for
PAL BGHI, PAL N, combination PAL N, PAL M,
NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and
SECAM
•
User programmable luminance peaking or aperture
correction
•
Cross-colour reduction for NTSC by chrominance comb
filtering
•
PAL delay line for correcting PAL phase errors
•
Brightness Contrast Saturation (BCS) and hue control
on-chip
•
Real-time status information output (RTCO)
•
Two multi functional real-time output pins controlled by
I
2
C-bus
•
Multi-standard VBI-data slicer decoding World Standard
Teletext (WST), North-American Broadcast Text
System (NABTS), closed caption, Wide Screen
Signalling (WSS), Video Programming System (VPS),
Vertical Interval Time Code (VITC) variants
(EBU/SMPTE) etc.
•
Standard ITU 656 YUV 4 : 2 : 2 format (8-bit) on VPO
output bus
•
Enhanced ITU 656 output format on VPO output bus
containing:
– active video
– raw CVBS data for INTERCAST applications
(27 MHz data rate)
– decoded VBI data
•
Boundary scan test circuit complies with the
“IEEE Std.
1149.b1 - 1994”
(ID-Code = 1 7113 02B)
•
I
2
C-bus controlled (full read-back ability by an external
controller, bit rate up to 400 kbits/s)
•
Low power (<0.5 W), low voltage (3.3 V), small package
(QFP44)
•
Power saving mode by chip enable input
•
Detection of copy protected input signals according to
the macrovision standard. Can be used to prevent
unauthorized recording of pay-TV or video tape signals.
2
APPLICATIONS
•
Notebook (low power consumption)
•
PCMCIA card application
•
AGP based graphics cards
•
Image processing
•
Video phone applications
•
Intercast and PC teletext applications
•
Security applications.
2000 May 08
3
Philips Semiconductors
Product specification
9-bit video input processor
3
GENERAL DESCRIPTION
SAF7113H
The integrated high performance multi-standard data
slicer supports several VBI data standards:
•
Teletext [WST (World Standard Teletext), CCST
(Chinese teletext)] (625 lines)
•
Teletext [US-WST, NABTS (North-American Broadcast
Text System) and MOJI (Japanese teletext)] (525 lines)
•
Closed caption [Europe, US (line 21)]
•
Wide Screen Signalling (WSS)
•
Video Programming Signal (VPS)
•
Time codes (VITC EBU/SMPTE)
•
HIGH-speed VBI data bypass for intercast application.
The 9-bit video input processor is a combination of a
two-channel analog preprocessing circuit including source
selection, anti-aliasing filter and ADC, an automatic clamp
and gain control, a Clock Generation Circuit (CGC), a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
combination PAL N, NTSC M, NTSC-Japan, NTSC N and
SECAM), a brightness, contrast and saturation control
circuit, a multi-standard VBI data slicer and a 27 MHz
VBI data bypass; see Fig.1.
The pure 3.3 V CMOS circuit SAF7113H, analog front-end
and digital video decoder, is a highly integrated circuit for
desktop video applications. The decoder is based on the
principle of line-locked clock decoding and is able to
decode the colour of PAL, SECAM and NTSC signals into
ITU-R BT.601 compatible colour component values. The
SAF7113H accepts as analog inputs CVBS or S-video
(Y/C) from TV or VTR sources. The circuit is I
2
C-bus
controlled.
4
QUICK REFERENCE DATA
SYMBOL
V
DDD
V
DDA
T
amb
P
A+D
5
PARAMETER
digital supply voltage
analog supply voltage
operating ambient temperature
analog and digital power dissipation
MIN.
3.0
3.1
−40
−
3.3
3.3
+25
0.4
TYP.
3.6
3.5
+85
−
MAX.
V
V
°C
W
UNIT
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SOT307-2
SAF7113H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10
×
10
×
1.75 mm
2000 May 08
4
Philips Semiconductors
Product specification
9-bit video input processor
6
BLOCK DIAGRAM
SAF7113H
handbook, full pagewidth
MULTI-STANDARD DATA SLICER
4
5
7
9
43
44
1
AD2 AD1
6
CON
ANALOG
PROCESSING
CONTROL
Y
Y/CVBS
LUMINANCE
CIRCUIT
I
2
C-BUS CONTROL
I
2
C-BUS
INTERFACE
23
SDA
24
SCL
ANALOG
PROCESSING
AND
ANALOG-TO-
DIGITAL
CONVERSION
C/CVBS
AI11
AI1D
AI12
AOUT
AI21
AI2D
AI22
AGND
VBI DATA BYPASS
UPSAMPLING FILTER
bypass
UV
Y
OUTPUT
FORMATTER
12 to 15,
19 to 22
VPO7
to
VPO0
CHROMINANCE
CIRCUIT
AND
BRIGHTNESS CONTRAST
SATURATION CONTROL
SAF7113H
VSSA1
VSSA2
VDDA1
VDDA2
TDI
TCK
TMS
TRST
TDO
2
41
3
42
38
37
39
8
36
Y
TEST
CONTROL BLOCK
FOR
BOUNDARY
SCAN TEST
AND
SCAN TEST
18
29
33
34
16
28
CLOCKS
SYNCHRONIZATION
CIRCUIT
LFCO
CLOCK
GENERATION
CIRCUIT
POWER-ON
CONTROL
10
11
40
31
32
XTAL
XTALI
17
LLC
30
35
26
27
25
MHB690
VDDDE1
VDDDA
VSSDE1
VDDDI
VDDDE2
VSSDA
RTS0 RTS1 RTCO
VSSDI
VSSDE2
VDDA0 VSSA0 CE
Fig.1 Block diagram.
2000 May 08
5
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