Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
FEATURES
•
Integrated buffers for simple interfacing to analog inputs
•
4 flexible serial interface modes
•
Overload detection of digital signal
≥−1
dB amplitude
•
Selectable high-pass filter
•
18-bit serial output
•
3.4 to 5.5 V operation of digital part
•
Standby mode
•
SO24 package
•
Small non-critical PCB layout.
GENERAL DESCRIPTION
The SAA7366 is a CMOS cost effective stereo
analog-to-digital converter (ADC) using the Philips
bitstream conversion technique.
QUICK REFERENCE DATA
SYMBOL
V
DDD
V
DDA
f
i
THD + N
DR
PARAMETER
digital supply voltage
analog supply voltage
clock input frequency
total harmonic distortion + noise
dynamic range
3.4
4.5
4.608
−
90
MIN.
5.0
5.0
12.288
−
−
TYP.
5.5
5.5
13.568
−80
−
MAX.
APPLICATIONS
SAA7366
The device is designed for digital acquisition of analog
audio signals for digital audio systems such as:
•
CD-recordable
•
Digital Compact Cassette (DCC)
•
Digital Audio Tape (DAT).
UNIT
V
V
MHz
dB
dB
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
SAA7366T
(1)
Note
1. Plastic small outline package; 24 leads; body width 7.5 mm; (SOT137A); SOT137-1; 1996 Oct 29.
24
PIN POSITION
SO24L
MATERIAL
plastic
CODE
SOT137A
May 1994
2
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
PINNING
SYMBOL
SFOR
STD
OVLD
CKIN
V
DDD
V
SSD
SDO
SWS
PIN
1
2
3
4
5
6
7
8
DESCRIPTION
SAA7366
Serial interface output format select. Output format is selected as follows: SFOR
HIGH = Format 1; SFOR LOW = Format 2.
Standby mode input (active LOW).
Overload indication output. This pin indicates whether the internal digital signal is within 1 dB
of maximum. In standby mode this output is high impedance.
System clock input.
Supply for the digital section (3.4 to 5.5 V).
Ground supply for the digital section.
Serial interface data output. In standby mode this output is high impedance.
Serial interface word select signal. In master mode this pin outputs the serial interface word
select signal. In slave mode this pin is the word select input to the serial interface. In standby
mode this pin is always an input (high impedance).
Serial interface clock. In master mode this pin outputs the serial interface bit clock. In slave
mode this pin is the input for the external bit clock. In standby mode this output is
high impedance.
Test input 1. This pin should be left open-circuit.
High-pass filter enable input. (HPEN HIGH = enabled). If unconnected this pin defaults HIGH.
Test input 2. This pin should be left open-circuit.
Ground supply for the analog section.
Current reference output node.
1
⁄
2
V
DDA
SCK
9
TEST1
HPEN
TEST2
V
SSA
I
REF
V
REFR
BIR
BOR
V
DACN
V
DACP
BOL
BIL
V
REFL
V
DDA
SLAVE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
reference generator output for the right channel analog section.
Buffer operational amplifier inverting input for right channel.
Buffer operational amplifier output for right channel.
Negative 1-bit DAC reference voltage input, connected to 0 V.
Positive 1-bit DAC reference voltage input, connected to +5 V.
Buffer operational amplifier output for left channel.
Buffer operational amplifier inverting input for left channel.
1
⁄
2
V
DDA
reference generator output for the left channel analog section.
Supply for the analog section.
Serial interface operating output mode master/slave select as follows: HIGH = slave mode;
LOW = master mode. If unconnected the pin will default LOW.
May 1994
4
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for
digital audio systems
SAA7366
respectively. By the choice of feedback component values,
the application signal amplitude can be matched to the
requirements of the ADC. Typically the operational
amplifiers are configured as low-pass filters with a gain
of 1 and a pole at approximately 5f
s
.
Remark:
The complete ADC is non-inverting. Hence a
positive DC input (referenced to V
ref
) will yield a positive
digital output.
Input level
The overall system gain is proportional V
DDA
, or more
accurately {V(V
DACP
)
−
V(V
DACN
)}. For convenience the
ADC input signal amplitude is defined as that amplitude
seen on BOL or BOR, the operational amplifier outputs
(i.e. the input to the Sigma-Delta modulator). Also, the
0 dB input level is defined as that which provides a
−1
dB
(actually
−1.08
dB) digital output, relative to full-scale
swing. This offset provides headroom to accommodate
small random DC offsets without causing the digital output
to clip.
Hence:
V
(
V
DACP
)
–
V
(
V
DACN
)
V
I
(
0 dB
)
=
---------------------------------------------------------------
=
V (RMS)
-
5
The user of the IC should ensure, that when all sources of
signal amplitude variation are taken into account, the
maximum input signal should conform to the 0 dB level. If
not, clipping may occur. In the event that the maximum
signal level cannot be pre-determined, e.g. a live
microphone input, the average signal level should be set
at
−10
to
−20
dB down. The exact value will depend on the
application and the balance between head room and
operating signal-to-noise ratio.
Behaviour during overload
As defined earlier the maximum input level for normal
operation is 0 dB. If the input level exceeds this value
clipping may occur. Infringements are limited to the
maximum permitted positive or negative values, 2
17
−
1 or
−2
17
respectively. If the high-pass filter has been enabled
the clipped output samples may have non-maximum
values due to the removal of the DC content. Input signals
in the range of 0 to 1 dB may or may not be clipped
depending on the values of DC dither and small random
offsets in the analog circuitry.
When using the recommended application circuitry,
clipping will initially be observed on negative peaks due to
the use of negative DC dither.
The maximum level of overload that can be safely
tolerated is application circuit dependent. In the case of the
SFOR
STD
OVLD
CKIN
V DDD
VSSD
SDO
SWS
SCK
1
2
3
4
5
6
SAA7366
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
MGA912
SLAVE
VDDA
VREFL
BIL
BOL
V DACP
VDACN
BOR
BIR
VREFR
I REF
VSSA
TEST1 10
HPEN 11
TEST2 12
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
General
The SAA7366 is a bitstream conversion CMOS ADC for
digital audio systems. The conversion is achieved using a
third order Sigma-Delta modulator (SDM), operating at
128 times the output sample frequency (f
s
). The high
oversampling ratio greatly simplifies the design of the
analog input anti-alias filter. In most cases the internal
buffer operational amplifier, configured as a low-pass filter
will suffice. The 1-bit code from the Sigma-Delta modulator
is filtered and down-sampled (decimated) to 1f
s
in two
stages of filtering. An optional high-pass filter is provided
to remove DC, if required. The device has been designed
with ease of use, low board area and low application costs
in mind.
Clock frequency
The external clock, input on pin CKIN, operates at
256 times f
s
, which can range from 18 kHz to 53 kHz.
Input buffer
Two input buffers are provided, one for each channel, for
signal amplitude matching, signal buffering and anti-alias
filter purposes. These are configured for inverting use.
Access is provided by pins BIL, BIR (inverting inputs) and
BOL, BOR (outputs) for left and right channels
May 1994
5
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