PRTR5V0U8S
Integrated octal low-capacity ESD protection to IEC 61000-4-2
level 4
Rev. 01 — 14 January 2008
Preliminary data sheet
1. Product profile
1.1 General description
The PRTR5V0U8S is designed to protect Input/Output (I/O) ports that are sensitive
concerning capacitive load, such as USB 2.0, Ethernet, Digital Video Interface (DVI), etc.
from destruction by ElectroStatic Discharges (ESD).
Therefore, the PRTR5V0U8S incorporates eight pairs of ultra-low capacity rail-to-rail
diodes plus an additional Zener diode to provide protection to downstream signal and
supply components from ESD voltages as high as
±8
kV contact discharge.
Due to the rail-to-rail diodes being connected to the Zener diode, the protection is working
independent from the availability of a supply voltage.
The PRTR5V0U8S is fabricated using thin film-on-silicon technology and integrates eight
pairs of ultra-low capacity rail-to-rail ESD protection diodes in a miniature 10-lead
TSSOP10 package.
1.2 Features
I
I
I
I
I
I
I
I
Pb-free and RoHS (Restriction of Hazardous Substances) compliant, dark green
ESD protection of up to eight Hi-Speed data lines or high-frequency signal lines
Eight pairs of ESD rail-to-rail protection diodes
Ultra-low input capacitance: C
(I/O-GND)
= 1 pF
ESD protection up to 8 kV (contact discharge compliant)
IEC 61000-4-2, level 4 (ESD)
Low voltage clamping due to an integrated protection Zener diode
Small TSSOP10 (SOT552-1) package
1.3 Applications
I
General-purpose downstream ESD protection high-frequency analog signals and
high-speed serial data transmission for ports inside:
N
Cellular and Personal Communication System (PCS) mobile handsets
N
USB 2.0 ports in PC or Notebook
N
IEEE 1394 ports
N
Digital Video Interface (DVI) and High Definition Multimedia Interface (HDMI)
N
Cordless telephones
N
Wireless data: Wide Area Network (WAN) and Local Area Network (LAN) systems
N
Personal Digital Assistants (PDAs)
NXP Semiconductors
PRTR5V0U8S
Integrated octal low-capacity ESD protection
2. Pinning information
Table 1.
Pin
1
2
3
4
5
6
7
8
9
10
Pinning
Simplified outline
10
6
1
10
Description
ESD protection I/O 1
ESD protection I/O 2
ground (GND)
ESD protection I/O 3
ESD protection I/O 4
ESD protection I/O 5
ESD protection I/O 6
supply voltage (V
CC
)
ESD protection I/O 7
ESD protection I/O 8
Symbol
2
9
3
8
1
5
4
7
5
6
001aah386
3. Ordering information
Table 2.
Ordering information
Package
Name
PRTR5V0U8S
TSSOP10
Description
plastic thin shrink small outline package; 10 leads;
body width 3 mm
Version
SOT552-1
Type number
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
(I/O-GND)
T
stg
Table 4.
Standard
Per diode
IEC 61000-4-2; level 4 (ESD)
≤
8 kV (contact)
Parameter
input/output to ground voltage
storage temperature
ESD standards compliance
Conditions
Conditions
Min
0
−55
Max
5.5
+125
Unit
V
°C
PRTR5V0U8S_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 14 January 2008
2 of 7
NXP Semiconductors
PRTR5V0U8S
Integrated octal low-capacity ESD protection
5. Recommended operating conditions
Table 5.
Symbol
T
amb
Operating conditions
Parameter
ambient temperature
Conditions
Min
−40
Typ
-
Max
+85
Unit
°C
6. Characteristics
Table 6.
Characteristics
T
amb
= 25
°
C unless otherwise specified.
Symbol
Parameter
Conditions
V
I
= 0 V; f = 1 MHz; V
CC
= 3 V
V
I
= 3 V
I
I
= 1 mA
V
I
= 0 V; f = 1 MHz; V
CC
= 3 V
[1]
Min
-
-
6
-
-
Typ
1.0
-
-
30
0.7
Max
-
100
9
-
-
Unit
pF
nA
V
pF
V
Protection diodes
C
(I/O-GND)
input/output to ground
capacitance
I
LR
V
BR
C
sup
V
F
[1]
[2]
reverse leakage current
breakdown voltage
supply pin to ground
capacitance
forward voltage
[1]
Zener diode
[2]
[2]
Measured from pin 1, 2, 4, 5, 6, 7, 9 and 10 to ground
Measured from pin 8 to ground
PRTR5V0U8S_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 14 January 2008
3 of 7
NXP Semiconductors
PRTR5V0U8S
Integrated octal low-capacity ESD protection
7. Package outline
TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm
SOT552-1
D
E
A
X
c
y
HE
v
M
A
Z
10
6
A2
pin 1 index
A1
(A3)
A
θ
Lp
L
1
e
bp
5
detail X
w
M
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
max.
1.1
A1
0.15
0.05
A2
0.95
0.80
A3
0.25
bp
0.30
0.15
c
0.23
0.15
D
(1)
3.1
2.9
E
(2)
3.1
2.9
e
0.5
HE
5.0
4.8
L
0.95
Lp
0.7
0.4
v
0.1
w
0.1
y
0.1
Z
(1)
0.67
0.34
θ
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT552-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-07-29
03-02-18
Fig 1. Package outline SOT552-1 (TSSOP10)
PRTR5V0U8S_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 14 January 2008
4 of 7
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