Features
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Saifun NROM™ Cell
Serial Peripheral Interface (SPI) Compatible,
Supports SPI Modes 0 (0,0) and 3 (1,1)
Byte and Page Write Operation:
1024 pages (256 Bytes/Page)
Single Byte or Page Write Cycle in 10ms Typical
Single Supply Voltage: 2.7V to 3.6V
25MHz Clock Rate
Block Write Protection: Protect Quarter, Half or Entire Array
Write Protect Pin and Write Disable Instructions of Both
Hardware and Software Data Protection
100,000 Erase Cycles (Minimum)
More than 20-Year Data Retention
Low-power Standby Current (less than 1µA)
8-SOIC Narrow Package
MLF Leadless Package
Temperature Range:
Industrial: -40°C to +85°C
Commercial: 0°C to +70°C
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SA25C020
Advanced
Information
2Mb EEPROM with
25MHz SPI Bus
Interface
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http://www.saifun.com
Saifun NROM
TM
is a trademark of Saifun Semiconductors Ltd.
This Data Sheet states Saifun's current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
1911
Rev:
0
Amendment:
0
Issue Date:
20 July 2003
SA25C020 Advanced Information
SAIFUN
2
General Description
The SA25C020 is a 2Mb (512K X 4) CMOS
non-volatile serial EEPROM. This device
fully conforms to the SPI 4-wire protocol, is
enabled through the Chip Select (CSb) pin,
and uses Clock (SCK), Data-in (SI) and
Data-out (SO) pins to synchronously control
data
transfer
between
the
SPI
microcontroller and the Serial EEPROM.
The memory can be written from 1 up to
256 bytes at a time via the Byte / Page
Write (PW) instruction.
The memory consists of 1024 pages or
262,144 bytes.
Each device requires only a 3.0V power
supply (2.7 V to 3.6 V) for both read and
write functions. Internally generated and
regulated voltages are provided for the
program and erase operations. The
SA25C020 does not require a V
PP
supply.
The HOLDb pin may be used to suspend
any serial communication without resetting
the serial sequence. In addition, the serial
interface allows a minimal-pin-count
packaging designed to simplify PC board
layout requirements and offers the designer
a variety of low-voltage and low-power
options.
The SA25C020 is available in a
space-saving, 8-lead narrow SOIC package
The SA25C020 is part of the SPI EEPROM
family. It is designed to work with any SPI-
compatible, high-speed microcontroller, and
offers both hardware (WPb pin) and
Software (“block protect”) data protection.
For example, programming a 2-bit code into
the status register prevents program with
top ¼, top ½ or entire array write protection
and enables block write protection.
Separate program enable and program
disable instructions are provided for
additional data protection. Hardware data
protection is provided via the WPb pin to
protect against inadvertent write attempts to
the status register.
Saifun’s SPI Serial EEPROM products are
designed and tested for applications
requiring high endurance and low power
consumption for a continuously reliable
non-volatile solution for all markets.
SA25C020 Advanced Information
SAIFUN
3
Table of Contents
Features ........................................................................... 1
General Description ........................................................ 2
Memory Organization...................................................... 5
Connection Diagrams ..................................................... 6
Ordering Information ...................................................... 7
Product Specifications ................................................... 8
Absolute Maximum Ratings....................................... 8
ESD/Latch Up Specification (JEDEC 8 Spec) ........... 8
Operating Conditions................................................. 8
DC Characteristics .......................................................... 9
AC Test Conditions ....................................................... 10
Timing Diagrams ........................................................... 11
Signal Description......................................................... 13
Chip Select (CSb).................................................... 13
Serial Clock (SCK) .................................................. 13
Serial Input (SI) ....................................................... 13
Serial Output (SO)................................................... 13
Hold (HOLDb).......................................................... 13
Write Protect (WPb) ................................................ 13
Serial Interface Description .......................................... 14
SPI Modes............................................................... 14
Master ............................................................. 14
Slave ............................................................... 14
Transmitter/Receiver ....................................... 14
Serial Opcode.................................................. 14
Invalid Opcode ................................................ 14
Chip Select (CSb)............................................ 15
Hold Condition................................................. 15
Write Protect ................................................... 16
Functional Description ................................................. 17
Instructions.............................................................. 17
Read Status Register (RDSR) ................................. 18
Write Enable (WREN) ............................................. 20
Write Disable (WRDI).............................................. 20
Write Status Register (WRSR) ................................ 21
Read Data Bytes (READ) ........................................ 23
Byte or Page Write (PW)......................................... 24
Read Electronic Signature (Read_Id) ...................... 26
Powerup and Powerdown ........................................ 27
Physical Dimensions..................................................... 28
Contact Information ...................................................... 31
Life Support Policy........................................................ 31
SA25C020 Advanced Information
SAIFUN
4
List of Figures
Figure 1. SA25C020 Block Diagram................................ 5
Figure 2. SOIC 8 (150 mil)/PDIP/MLF Package
(Top View) ............................................................. 6
Figure 3. SA25C020 Ordering Information ...................... 7
Figure 4. SPI Mode 0 (0,0) Input Timing........................ 11
Figure 5. SPI Mode 0 (0,0) Output Timing ..................... 11
Figure 6. AC Measurements I/O Waveform................... 12
Figure 7. Supported SPI Modes .................................... 14
Figure 8. Hold Condition................................................ 15
Figure 9. SPI Serial Interface ........................................ 17
Figure 10. Read Status Register (RDSR) Instruction
Sequence ............................................................ 19
Figure 11. Write Enable (WREN) Instruction Sequence 20
Figure 12. Write Disable (WRDI) Instruction Sequence. 20
Figure 13. Write Status Register (WRSR) Instruction
Sequence ............................................................ 22
Figure 14. Read (READ) Instruction Sequence ............. 23
Figure 15. Byte or Page Write (PW) Instruction
Sequence ............................................................ 25
Figure 16. Read Electronic Signature (Read Id) Instruction
Sequence ............................................................ 26
Figure 17. 8-pin SOIC Package..................................... 28
Figure 18. 8-pin MLF Leadless Package ....................... 29
Figure 19. Molded Dual-in-line Package (N) Package
Number N08E...................................................... 30
List of Tables
Table 1. Pin Names......................................................... 6
Table 2. DC Characteristics............................................. 9
Table 3. AC Test Conditions.......................................... 10
Table 4. AC Measurements........................................... 12
Table 5. Instruction Set ................................................. 17
Table 6. Status Register Format.................................... 17
Table 7. Read Status Register Definition....................... 18
Table 8. Block Write Protect Bits................................... 21
Table 9. WPBEN Operation .......................................... 21
Table 10. Powerup ........................................................ 27
SA25C020 Advanced Information
SAIFUN
5
Memory Organization
The memory is organized in the following
manner:
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262,144 bytes (8 bits each)
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1024 pages (256 bytes each)
Each byte or page can be individually
written with the bits programmed from
1 to 0 and from 0 to 1.
SRAM
PS
Array - L
Logic
X
D
E
C
Array - R
RD
DATA PATH
IO
HOLDb
GND
Figure 1. SA25C020 Block Diagram
WPb
SCK
CSb
Vcc
SO
SI
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