User’s Manual
32
V850ES/JH3-E, V850ES/JJ3-E
User’s Manual: Hardware
RENESAS MCU
V850ES/Jx3-E Microcontrollers
V850ES/JH3-E
μPD70F3778
μPD70F3779
μPD70F3780
μPD70F3781
μPD70F3782
μPD70F3783
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
V850ES/JH3-H
μPD70F3784
μPD70F3785
μPD70F3786
www.renesas.com
Rev.3.00
Sep, 2011
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
When exporting the products or technology described in this document, you should comply with the applicable export control
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does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
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“Standard”:
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
How to Use This Manual
Readers
This manual is intended for users who wish to understand the functions of the
V850ES/JH3-E
and
V850ES/JJ3-E
and
design
application
systems
using
the
V850ES/JH3-E and V850ES/JJ3-E.
Purpose
This manual is intended to give users an understanding of the hardware functions of the
V850ES/JH3-E and V850ES/JJ3-E shown in the
Organization
below.
Organization
The manual of these products is divided into two volumes: Hardware (this volume) and
Architecture (V850ES
Architecture User’s Manual).
Hardware
•
Pin functions
•
CPU function
•
On-chip peripheral functions
•
Flash memory programming
•
Electrical specifications
How to Read This Manual
Architecture
•
Data types
•
Register set
•
Instruction format and instruction set
•
Interrupts and exceptions
•
Pipeline operation
It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850ES/JH3-E and V850ES/JJ3-E
→
Read this manual according to the
CONTENTS.
Register format
→
The name of the bit whose number is in angle brackets (<>) in the figure of the register
format of each register is defined as a reserved word in the device file.
To understand the details of an instruction function
→
Refer to the
V850ES Architecture User’s Manual
available separately.
To know the electrical specifications of the V850ES/JH3-E and V850ES/JJ3-E
→
Refer to the
CHAPTER 35 ELECTRICAL SPECIFICATIONS.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with
caution that if “xxx.yyy” is described as is in a program, however, the compiler/assembler
cannot recognize it correctly.
The mark <R> shows major revised points. The revised points can be easily searched
by copying an “<R>” in the PDF file and specifying it in the “Find what: ” field.
Conventions
Data significance:
Active low representation:
Memory map address:
Note:
Caution:
Remark:
Numeric representation:
Higher digits on the left and lower digits on the right
xxx (overscore over pin or signal name)
Higher addresses on the top and lower addresses on the
bottom
Footnote for item marked with
Note
in the text
Information requiring particular attention
Supplementary information
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2
(address space, memory
capacity):
K (kilo): 2
10
= 1,024
M (mega): 2
20
= 1,024
2
G (giga): 2
30
= 1,024
3
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