PI6C48545
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVDS Fanout Buffer
Features
•
•
•
•
•
•
•
•
•
•
•
Maximum operation frequency: 650 MHz
4 pair of differential LVDS outputs
Selectable CLK
0
and CLK
1
inputs
CLK
0
, CLK
1
accept LVCMOS, LVTTL input level
Output Skew: 40ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 2.2ns (maximum)
3.3V power supply
Pin-to-pin compatible to ICS8545
Operating Temperature: -40
o
C to 85
o
C
Packaging (Pb-free & Green):
- 20-pin TSSOP (L)
Description
The PI6C48545 is a high-performance low-skew LVDS fanout
buffer. PI6C48545 features two selectable single-ended clock in-
puts and translate to four LVDS outputs. The CLK
0
and CLK
1
inputs accept LVCMOS or LVTTL signals. The outputs are
synchronized with input clock during asynchronous assertion/
deassertion of CLK_EN pin. PI6C48545 is ideal for single-ended
LVTTL/LVCMOS to LVDS translations. Typical clock transla-
tion and distribution applications are data-communications and
telecommunications.
Block Diagram
CLK_EN
D
LE
CLK
0
CLK
1
0
1
Q
0
n
Q
0
Q
1
n
Q
1
CLK_SEL
Q
2
n
Q
2
Q
3
n
Q
3
Q
Pin Diagram
GND
CLK_EN
CLK_SEL
CLK
0
NC
CLK
1
NC
OE
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q
0
nQ
0
V
CC
Q
1
nQ
1
Q
2
nQ
2
GND
Q
3
nQ
3
OE
1
PS8770
06/23/05
PI6C48545
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVDS Fanout Buffer
Pin Description
Name
GND
CLK_EN
CLK_SEL
CLK
0
CLK
1
NC
OE
V
CC
Q
3
,
n
Q
3
Q
2
,
n
Q
2
Q
1
,
n
Q
1
Q
0
,
n
Q
0
Pin #
1, 9, 13
2
3
4
6
5, 7
8
10, 18
11, 12
14, 15
16, 17
19, 20
I_PU
P
O
O
O
O
Type
P
I_PU
I_PD
I_PD
I_PD
Connect to Ground
Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx
outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 80kΩ
pull up.
Clock select input. When high, selects CLK
1
input. When low, selects CLK
0
input.
LVCMOS/LVTTL level with 80kΩ pull down.
LVCMOS / LVTTL clock input
LVCMOS / LVTTL clock input
No internal connection.
Output Enable. Controls outputs Q
0
,
n
Q
0
through Q
3
, nQ
3.
Connect to 3.3V.
Differential output pair, LVDS interface level.
Differential output pair, LVDS interface level.
Differential output pair, LVDS interface level.
Differential output pair, LVDS interface level.
Description
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up.
Pin Characteristics
Symbol
C
IN
R_pullup
R_pulldown
Parameter
Input Capacitance
Input Pullup Resistance
Input Pulldown Resistance
Conditions
Min.
Typ.
6
80
80
Max.
Units
pF
kΩ
Control Input Function Table
Inputs
OE
1
1
1
1
0
CLK_EN
0
0
1
1
x
CLK_SEL
0
1
0
1
x
Selected Source
CLK
0
CLK
1
CLK
0
CLK
1
Q
0
:Q
3
Diasbled: Low
Disabled: Low
Enabled
Enabled
HiZ
Outputs
n
Q
0
:
n
Q
3
Diasbled: High
Disabled: High
Enabled
Enabled
HiZ
Notes:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
2
PS8770
06/23/05
PI6C48545
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVDS Fanout Buffer
Figure 1. CLK_EN Timing Diagram
Disabled
Enabled
CLK
0
CLK
1
CLK_EN
nQ0:nQ3
Q0:Q3
Clock Input Function Table
Inputs
CLK
0
or CLK
1
0
1
Q
0
:Q
3
LOW
HIGH
Outputs
n
Q
0
:
n
Q
3
HIGH
LOW
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
OUT
T
STG
Parameter
Supply voltage
Input voltage
Output voltage
Storage temperature
Conditions
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
Min.
Typ.
Max.
4.6
V
CC
+0.5V
V
CC
+0.5V
150
V
o
C
Units
Notes:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci
fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Conditions
Symbol
V
CC
T
A
I
CC
Parameter
Power Supply Voltage
Ambient Temperature
Power Supply Current
Conditions
Min.
3.135
-40
Typ.
3.3
Max.
3.465
85
60
Units
V
o
C
mA
3
PS8770
06/23/05
PI6C48545
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVDS Fanout Buffer
LVCMOS/LVTTL DC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.135V to 3.465V unless otherwise stated below.)
Symbol
V
IH
V
IL
I
IH
I
IL
Input High
Voltage
Input Low
Voltage
Input High
Current
Input Low
Current
Parameter
CLK
0
, CLK
1
, CLK_EN,
CLK_SE, OE
CLK
0
, CLK
1
CLK_EN, CLK_SEL, OE
CLK0, CLK1, CLK_SEL
CLK_EN, OE
CLK
0
, CLK
1
, CLK_SEL
CLK_EN, OE
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-5
-150
Conditions
Min.
2
-0.3
-0.3
Typ.
Max.
V
CC
+0.3
1.3
0.8
150
5
Units
V
V
V
uA
uA
uA
uA
LVDS DC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.135V to 3.465V unless otherwise stated below.)
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
I
OZ
I
OFF
I
OSD
I
OS
V
OH
V
OL
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
High Impedance Leakage Current
Power OFF Leakage
Differential Output Short Circuit Current
Output Short Circuit Current
Output Voltage High
Output Voltage Low
0.9
-10
-20
±1
-3.5
-3.5
1.34
1.06
1.125
Conditions
Min.
200
Typ.
280
0
1.3
5
Max.
360
40
1.475
25
+10
+20
-5
-5
1.6
Units
mV
V
mV
µA
mA
V
AC Characteristics
(T
A
= -40
o
C to 85
o
C, V
CC
= 3.135V to 3.465V)
Symbol
f
max
t
Pd
T
sk(o)
T
sk(pp)
t
r
/t
f
odc
Parameter
Output Frequency
Propagation Delay
(1)
Output-to-output Skew
(2)
Part-to-part Skew
(3)
Output Rise/Fall time
Output duty cycle
20% - 80%
100
48
0.8
Conditions
Min.
Typ.
Max.
650
2.2
40
300
300
52
%
ps
Units
MHz
ns
Notes:
1. Measured from the V
CC
/2 of the input to the differential output crossing point
2. Defined as skew between outputs at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point.
3. Defined as skew between outputs on different parts operating at the same supply voltage and with equal load condition. Measured at the
outputs differential crossing point.
4. All parameters are measured at 500MHz unless noted otherwise
4
PS8770
06/23/05
PI6C48545
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVDS Fanout Buffer
Packaging Mechanical: 20-Pin TSSOP (L)
20
.169
.177
4.3
4.5
1
.252
.260
6.4
6.6
.004
0.09
.008
0.20
.047
1.20
Max
SEATING
PLANE
0.45
0.75
.018
.030
.238
.269
6.1
6.7
.0256
BSC
0.65
.007
.012
0.19
0.30
.002
0.05
.006
0.15
Ordering Information
Ordering Code
PI6C48545LE
Package Code
L
Package Description
Pb-free & Green 20-pin 173-mil wide TSSOP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. Number of Transistors = TBD
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
5
PS8770
06/23/05
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