TECHNICAL DATA
IW4023B
Triple 3-Input NAND Gate
High-Voltage Silicon-Gate CMOS
The IW4023B NAND gates provide the system designer with direct
emplementation of the NAND function.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4023BN Plastic
IW4023BD SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
PIN 14 =V
CC
PIN 7 = GND
Inputs
A
L
X
X
H
B
X
L
X
H
C
X
X
L
H
Output
Y
H
H
H
L
X = don’t care
1
IW4023B
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
P
D
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +20
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±10
750
500
100
-65 to +150
260
Unit
V
V
V
mA
mW
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
3.0
0
-55
Max
18
V
CC
+125
Unit
V
V
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
IW4023B
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input A, B or C
to Output Y (Figure 1)
Maximum Output Transition Time, Any Output
(Figure 1)
Maximum Input Capacitance
V
5.0
10
15
5.0
10
15
-
250
120
90
200
100
80
Guaranteed Limit
≥-55°C
25°C
250
120
90
200
100
80
7.5
≤125°C
500
240
180
400
200
160
Unit
ns
t
TLH
, t
THL
ns
C
IN
pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/3 of the Device)
4
IW4023B
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
14
8
B
1
7
Dimensions, mm
Symbol
A
B
MIN
18.67
6.10
0.36
1.14
2.54
7.62
0°
2.92
7.62
0.20
0.38
10°
3.81
8.26
0.36
MAX
19.69
7.11
5.33
0.56
1.78
F
L
C
D
F
G
J
C
-T-
SEATING
N
G
D
0.25 (0.010) M T
K
PLANE
M
H
H
J
K
L
M
N
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum
mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC
(MS - 012AB)
A
14
8
Dimensions, mm
Symbol
.
A
MIN
8.55
3.80
1.35
0.33
0.40
1.27
5.72
0°
0.10
0.19
5.80
0.25
8°
0.25
0.25
6.20
0.50
MAX
8.75
4.00
1.75
0.51
1.27
H
B
P
B
C
D
C
R x 45
1
G
7
F
G
H
-T-
D
0.25 (0.010) M T C M
K
SEATING
PLANE
J
F
M
J
K
M
P
R
NOTES:
1.Dimensions A and B do not include mold flash or protrusion.
2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for
B - 0.25 mm (0.010) per side.
5
Microchip MCU
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