S75PL127JBDBAWU3 datasheet, PDF

Datasheet> All Categories > S75PL127JBDBAWU3

Preview

S75PL127JBDBAWU3: DescriptionPower supply woltage of 2.7 to 3.1 volt; File Size1MB，183 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

Download Datasheet View All

S75PL127JBDBAWU3 Overview

Power supply woltage of 2.7 to 3.1 volt

Preview

Download Datasheet

View All

S75PL127J MCPs

Stacked Multi-Chip Product (MCP)

CODE Flash, pSRAM and DATA Flash 128M (8M x 16-Bit CMOS 3.0 Volt-

Only, Simultaneous Operation, Page Mode CODE Flash Memory, with

64M/32M (4M/2M x 16-Bit) pSRAM and 512M/256/128M (32M/16M/8M x 16-

Bit) Data Flash Memory

ADVANCE

INFORMATION

Data Sheet

MCP Features

Power supply voltage of 2.7 to 3.1 volt

High Performance

— 65ns for PL-J, 70ns for pSRAM, and 110ns for GL-N

— Page access - 25ns

Package

— 9 x 12 mm 84 ball FBGA

Operating Temperature

— –25°C to +85°C (Wireless)

Other temperature grade options

— Please contact the factory through the local sales

support team

General Description

The 75PL Series is a product line of stacked Multi-Chip Product (MCP) packages

and consists of:

One S29PL127J based CODE Flash device(s)

pSRAM

One or more S29GLxxxN based DATA Flash device(s)

32M pSRAM

Code Flash

Density

128M

S75PL127JBD

Data Flash

256M

S75PL127JBE

512M

S75PL127JBF

64M pSRAM

Code Flash

Density

128M

S75PL127JCD

Data Flash

256M

S75PL127JCE

512M

S75PL127JCF

Publication Number

S75PL127J_00

Revision

Amendment

Issue Date

January 6, 2005

A d v a n c e

I n f o r m a t i o n

S75PL127J MCPs .................................................1

General Description ...................................................1

Product Selector Guide ............................................ 5

MCP Block Diagram ................................................ 6

Connection Diagram ................................................ 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information ............................................... 9

Valid Combinations .................................................10

Data: S29GL128N ................................................................................................ 10

Data: S29GL256N ................................................................................................ 11

Data: S29GL512N ............................................................................................... 12

Common Flash Memory Interface (CFI) ............ 40

Low VCC Write Inhibit ................................................................................ 39

Write Pulse “Glitch” Protection ............................................................... 39

Logical Inhibit ................................................................................................... 39

Power-Up Write Inhibit ............................................................................... 39

Table 9. CFI Query Identification String ................................ 40

Table 10. System Interface String ........................................ 41

Table 11. Device Geometry Definition ................................... 41

Table 12. Primary Vendor-Specific Extended Query ................ 42

Command Definitions .............................................44

Reading Array Data ...........................................................................................44

Reset Command .................................................................................................44

Autoselect Command Sequence .................................................................... 45

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................ 45

Word Program Command Sequence ........................................................... 45

Unlock Bypass Command Sequence ........................................................46

S29PL127J/S29PL064J/S29PL032J for MCP ..... 13

General Description .................................................15

Simultaneous Read/Write Operation with Zero Latency .......................15

Page Mode Features ............................................................................................15

Standard Flash Memory Features ....................................................................15

Chip Erase Command Sequence ................................................................... 47

Sector Erase Command Sequence ................................................................48

Erase Suspend/Erase Resume Commands ..................................................49

Command Definitions Tables .........................................................................50

Figure 4. Program Operation ............................................... 47

Figure 5. Erase Operation ................................................... 49

Table 13. Memory Array Command Definitions ...................... 50

Table 14. Sector Protection Command Definitions .................. 51

Pin Description .........................................................17

Device Bus Operations ............................................18

Table 1. PL127J Device Bus Operations ................................ 18

Requirements for Reading Array Data ......................................................... 18

Random Read (Non-Page Read) ................................................................ 18

Page Mode Read .............................................................................................. 19

Simultaneous Read/Write Operation ........................................................... 19

Write Operation Status ........................................ 52

DQ7: Data# Polling ............................................................................................ 52

RY/BY#: Ready/Busy# ........................................................................................55

DQ6: Toggle Bit I ............................................................................................... 55

DQ2: Toggle Bit II .............................................................................................. 56

Reading Toggle Bits DQ6/DQ2 ..................................................................... 56

DQ5: Exceeded Timing Limits ........................................................................ 57

DQ3: Sector Erase Timer ................................................................................ 57

Figure 7. Toggle Bit Algorithm ............................................. 56

Figure 6. Data# Polling Algorithm ........................................ 54

Table 2. Page Select .......................................................... 19

Table 3. Bank Select .......................................................... 19

Writing Commands/Command Sequences ................................................ 20

Accelerated Program Operation .............................................................. 20

Autoselect Functions .................................................................................... 20

Standby Mode .......................................................................................................20

Automatic Sleep Mode ...................................................................................... 21

RESET#: Hardware Reset Pin ......................................................................... 21

Output Disable Mode ........................................................................................ 21

Table 4. PL127J Sector Architecture ..................................... 22

Table 5. SecSiTM Sector Addresses ...................................... 27

Table 6. Autoselect Codes (High Voltage Method) .................. 28

Table 7. PL127J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 29

Table 8. Sector Protection Schemes ..................................... 30

Table 15. Write Operation Status ......................................... 58

Figure 8. Maximum Overshoot Waveforms ............................ 59

Absolute Maximum Ratings ...................................59

Operating Ranges ................................................... 60

Industrial (I) Devices ..........................................................................................60

Wireless Devices ................................................................................................60

Supply Voltages ...................................................................................................60

Autoselect Mode .................................................................................................27

Selecting a Sector Protection Mode ............................................................. 30

DC Characteristics .................................................. 61

Table 16. CMOS Compatible ................................................ 61

Sector Protection ................................................... 30

Sector Protection Schemes .................................. 30

Password Sector Protection ........................................................................... 30

WP# Hardware Protection ............................................................................ 30

Selecting a Sector Protection Mode ............................................................. 30

Persistent Protection Bit (PPB) ........................................................................31

Persistent Protection Bit Lock (PPB Lock) ..................................................31

Persistent Sector Protection Mode Locking Bit ........................................33

Password and Password Mode Locking Bit ................................................34

64-bit Password ...................................................................................................34

Write Protect (WP#) ........................................................................................34

Persistent Protection Bit Lock ....................................................................35

High Voltage Sector Protection ......................................................................35

Temporary Sector Unprotect .........................................................................37

AC Characteristic ....................................................62

Test Conditions .................................................................................................. 62

SWITCHING WAVEFORMS ......................................................................... 63

Figure 9. Test Setups ........................................................ 62

Table 17. Test Specifications ............................................... 62

Table 18. KEY TO SWITCHING WAVEFORMS .......................... 63

Figure 10. Input Waveforms and Measurement Levels ............ 63

Table 19. Read-Only Operations .......................................... 64

Figure 11. Read Operation Timings ...................................... 64

Figure 12. Page Read Operation Timings............................... 65

Table 20. Hardware Reset (RESET#) .................................... 65

Figure 13. Reset Timings .................................................... 66

Table 21. Erase and Program Operations .............................. 67

Figure 14. Program Operation Timings .................................

Figure 15. Accelerated Program Timing Diagram....................

Figure 16. Chip/Sector Erase Operation Timings ....................

Figure 17. Back-to-back Read/Write Cycle Timings.................

Figure 18. Data# Polling Timings (During Embedded

Algorithms).......................................................................

Figure 19. Toggle Bit Timings (During Embedded

Algorithms).......................................................................

Figure 20. DQ2 vs. DQ6 .....................................................

Persistent Sector Protection ................................. 31

VCC RampRate ................................................................................................... 63

Read Operations .................................................................................................64

Password Protection Mode ................................... 33

Reset ....................................................................................................................... 65

Erase/Program Operations .............................................................................. 67

Timing Diagrams .................................................................................................68

Figure 1. In-System Sector Protection/Sector

Unprotection Algorithms...................................................... 36

Figure 2. Temporary Sector Unprotect Operation .................... 37

SecSi™ (Secured Silicon) Sector Flash Memory Region ...........................37

Factory-Locked Area (64 words) ..............................................................37

Customer-Lockable Area (64 words) ......................................................38

SecSi Sector Protection Bits ........................................................................38

Hardware Data Protection ..............................................................................39

Figure 3. SecSi Sector Protect Verify..................................... 39

27631A5 September 28, 2004

A d v a n c e

I n f o r m a t i o n

Protect/Unprotect .................................................. 71

Table 22. Temporary Sector Unprotect ................................. 71

Figure 21. Temporary Sector Unprotect Timing Diagram.......... 71

Figure 22. Sector/Sector Block Protect and Unprotect

Timing Diagram ................................................................. 72

Table 23. Alternate CE# Controlled Erase and Program

Operations ....................................................................... 73

Table 24. Alternate CE# Controlled Write (Erase/Program) Opera-

tion Timings ..................................................................... 74

Table 25. Erase And Programming Performance .................... 75

Table 11. Primary Vendor-Specific Extended Query ............... 126

Command Definitions .......................................... 126

Reading Array Data ..........................................................................................127

Reset Command ................................................................................................127

Autoselect Command Sequence ...................................................................127

Enter Secured Silicon Sector/Exit Secured Silicon

Sector Command Sequence ...........................................................................128

Word Program Command Sequence ..........................................................128

Unlock Bypass Command Sequence .......................................................129

Write Buffer Programming .........................................................................129

Accelerated Program ...................................................................................130

Program Suspend/Program Resume Command Sequence ...................132

Controlled Erase Operations ..........................................................................73

BGA Pin Capacitance ............................................ 75

S29GLxxxN MirrorBit

Flash Family ........... 77

General Description ................................................78

Product Selector Guide ..........................................80

Block Diagram ........................................................ 81

Pin Description ....................................................... 82

Logic Symbol .......................................................... 83

S29GL512N ........................................................................................................83

S29GL256N .......................................................................................................83

S29GL128N .......................................................................................................83

Figure 1. Write Buffer Programming Operation .................... 131

Figure 2. Program Operation ............................................. 132

Figure 3. Program Suspend/Program Resume...................... 133

Figure 4. Erase Operation ................................................. 135

Chip Erase Command Sequence .................................................................. 133

Sector Erase Command Sequence ...............................................................134

Device Bus Operations ........................................... 84

Table 1. Device Bus Operations ........................................... 84

VersatileIO

) Control ............................................................................ 84

Requirements for Reading Array Data ........................................................ 84

Page Mode Read ............................................................................................. 85

Writing Commands/Command Sequences ................................................ 85

Write Buffer .................................................................................................... 85

Accelerated Program Operation .............................................................. 85

Autoselect Functions .................................................................................... 86

Standby Mode ...................................................................................................... 86

Automatic Sleep Mode ..................................................................................... 86

RESET#: Hardware Reset Pin ........................................................................ 86

Output Disable Mode ....................................................................................... 87

Erase Suspend/Erase Resume Commands ................................................. 135

Lock Register Command Set Definitions ...................................................136

Password Protection Command Set Definitions .....................................136

Non-Volatile Sector Protection Command Set Definitions .................138

Global Volatile Sector Protection Freeze Command Set .....................138

Volatile Sector Protection Command Set .................................................139

Secured Silicon Sector Entry Command ....................................................140

Secured Silicon Sector Exit Command .......................................................140

Command Definitions ....................................................................................... 141

Table 12. S29GL512N, S29GL256N, S29GL128N

Command Definitions, x16 ................................................ 141

Write Operation Status ..................................................................................144

DQ7: Data# Polling ...........................................................................................144

RY/BY#: Ready/Busy# ......................................................................................145

DQ6: Toggle Bit I ..............................................................................................146

Figure 5. Data# Polling Algorithm ...................................... 145

Figure 6. Toggle Bit Algorithm ........................................... 147

Table 2. Sector Address Table–S29GL512N ........................... 87

Table 3. Sector Address Table–S29GL256N ..........................102

Table 4. Sector Address Table–S29GL128N ..........................109

Table 5. Autoselect Codes, (High Voltage Method) ...............114

DQ2: Toggle Bit II .............................................................................................147

Reading Toggle Bits DQ6/DQ2 ....................................................................148

DQ5: Exceeded Timing Limits .......................................................................148

DQ3: Sector Erase Timer ...............................................................................148

DQ1: Write-to-Buffer Abort ..........................................................................149

Autoselect Mode ................................................................................................ 113

Table 13. Write Operation Status ....................................... 149

Figure 7. Maximum Negative Overshoot Waveform .............. 150

Figure 8. Maximum Positive Overshoot Waveform................ 150

Sector Protection ............................................................................................... 114

Persistent Sector Protection ...................................................................... 114

Password Sector Protection ....................................................................... 114

WP# Hardware Protection ........................................................................ 114

Selecting a Sector Protection Mode ........................................................ 114

Advanced Sector Protection .......................................................................... 115

Lock Register ....................................................................................................... 115

Persistent Sector Protection .......................................................................... 116

Dynamic Protection Bit (DYB) .................................................................. 116

Persistent Protection Bit (PPB) ................................................................. 117

Persistent Protection Bit Lock (PPB Lock Bit) ..................................... 117

Absolute Maximum Ratings ................................ 150

Operating Ranges ................................................. 150

DC Characteristics ................................................. 151

Test Conditions ......................................................152

Figure 9. Test Setup ........................................................ 152

Table 14. Test Specifications ............................................. 152

Table 6. Lock Register .......................................................116

Key to Switching Waveforms .............................. 152

AC Characteristics .................................................153

Read-Only Operations–S29GL128N, S29GL256N, S29GL512N .......... 153

Figure 11. Read Operation Timings .................................... 154

Figure 12. Page Read Timings ........................................... 154

Figure 10. Input Waveforms and Measurement Levels .......... 152

Table 7. Sector Protection Schemes ....................................118

Common Flash Memory Interface (CFI) ............ 122

Persistent Protection Mode Lock Bit ..........................................................118

Password Sector Protection ........................................................................... 119

Password and Password Protection Mode Lock Bit ............................... 119

64-bit Password .................................................................................................120

Persistent Protection Bit Lock (PPB Lock Bit) .........................................120

Secured Silicon Sector Flash Memory Region ..........................................120

Write Protect (WP#) ...................................................................................... 122

Hardware Data Protection ............................................................................ 122

Low VCC Write Inhibit .............................................................................. 122

Write Pulse “Glitch” Protection .............................................................. 122

Logical Inhibit ................................................................................................. 122

Power-Up Write Inhibit .............................................................................. 122

Table 8. CFI Query Identification String............................... 123

Table 9. System Interface String ........................................ 124

Table 10. Device Geometry Definition ................................. 125

Hardware Reset (RESET#) ............................................................................. 155

Erase and Program Operations–S29GL128N, S29GL256N,

S29GL512N ..........................................................................................................156

Figure 14. Program Operation Timings ...............................

Figure 15. Accelerated Program Timing Diagram..................

Figure 16. Chip/Sector Erase Operation Timings ..................

Figure 17. Data# Polling Timings (During Embedded

Algorithms).....................................................................

Figure 18. Toggle Bit Timings (During Embedded Algorithms)

Figure 19. DQ2 vs. DQ6 ...................................................

Figure 13. Reset Timings .................................................. 155

157

158

159

160

Alternate CE# Controlled Erase and Program Operations-

S29GL128N, S29GL256N, S29GL512N .........................................................161

September 28, 2004 27631A5

A d v a n c e

I n f o r m a t i o n

Erase And Programming Performance .............. 163

TSOP Pin and BGA Package Capacitance ......... 163

Figure 20. Alternate CE# Controlled Write (Erase/

Program) Operation Timings .............................................. 162

pSRAM Type 2 ................................................164

Features ................................................................ 164

Product Information ............................................ 164

Pin Description ..................................................... 164

Power Up Sequence ............................................. 165

Timing Diagrams ...................................................166

Power Up ............................................................................................................ 166

Figure 21. Power Up 1 (CS1# Controlled) ............................ 166

Figure 22. Power Up 2 (CS2 Controlled) .............................. 166

pSRAM Type 6 ................................................174

Features .................................................................

Pin Description .....................................................

Functional Description .........................................

Absolute Maximum Ratings ................................

DC Recommended Operating Conditions

(Ta = -40°C to 85°C) .............................................

DC Characteristics (Ta = -40°C to 85°C,

VDD = 2.6 to 3.3 V) (See Note 3 to 4) ................

Capacitance (Ta = 25°C, f = 1 MHz) ....................

AC Characteristics and Operating

Conditions .............................................................

Figure 29. Timing Waveform of Write Cycle(3)

(CS2 Controlled) ............................................................. 173

Figure 30. Timing Waveform of Write Cycle(4) (UB#, LB#

Controlled) ..................................................................... 173

174

175

176

Functional Description ........................................ 166

Absolute Maximum Ratings ................................. 167

DC Recommended Operating Conditions ......... 167

Capacitance (Ta = 25°C, f = 1 MHz) .................... 167

DC and Operating Characteristics ..................... 167

AC Operating Conditions ................................... 169

Common .............................................................................................................. 167

16M pSRAM .........................................................................................................168

32M pSRAM ........................................................................................................168

64M pSRAM ........................................................................................................ 169

Test Conditions (Test Load and Test Input/Output Reference) ....... 169

ACC Characteristics (Ta = -40°C to 85°C, V

= 2.7 to 3.1 V) ........ 170

Figure 23. Output Load ..................................................... 169

AC Test Conditions .............................................. 177

Timing Diagrams ................................................... 178

Read Timings .......................................................................................................178

Write Timings .................................................................................................... 180

Figure 1. Read Cycle ........................................................ 178

Figure 2. Page Read Cycle (8 Words Access) ....................... 179

Figure 3. Write Cycle #1 (WE# Controlled) (See Note 8) ...... 180

Figure 4. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 181

Figure 5. Deep Power Down Timing.................................... 181

Figure 6. Power-on Timing ................................................ 181

Figure 7. Read ................................................................ 182

(Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11) ............176

Timing Diagrams ....................................................171

Read Timings ....................................................................................................... 171

Figure 24. Timing Waveform of Read Cycle(1)...................... 171

Figure 25. Timing Waveform of Read Cycle(2)...................... 171

Figure 26. Timing Waveform of Read Cycle(2)...................... 171

Figure 27. Write Cycle #1 (WE# Controlled) ........................ 172

Figure 28. Write Cycle #2 (CS1# Controlled) ....................... 172

Deep Power-down Timing ..............................................................................181

Power-on Timing ................................................................................................181

Provisions of Address Skew ...........................................................................182

Read ...................................................................................................................182

Write .................................................................................................................182

Write Timings .................................................................................................... 172

Revision Summary .........................................183

Figure 8. Write ................................................................ 182

27631A5 September 28, 2004

Recommended Resources

Capacitive three-point sine wave oscillation circuit

Integrated phase-locked loop reference pulse generation (MC14046B)

TIL113/TIL119A type optocoupler circuit

KA2304 (toy) radio remote control reception control and regulation circuit

Relay application circuit of HT7605

Circuit diagram of 12V valve-controlled sealed lead-acid battery dual-level float charger UC3960

I have a very strange problem with the ADC12 module. Can anyone give me some advice? Thanks!: When I was self-studying the ADC12 conversion module of MSP430, I modified a small program according to the routine in a textbook, and then used the learning board + IAR to simulate it. As a result, a...; maogu Microcontroller MCU

Please help me with the problem of CAN not being able to communicate: At present, when debugging CAN communication on a terminal, there is a problem of abnormal communication (it is normal when debugging with J-LINK). After re-powering on 10 times, only one or two times...; wowow stm32/stm8

RFID-Automatic Wireless Identification and Data Acquisition Technology: RFID ( Radio Frequency Identification ) is an automatic wireless identification and data acquisition technology that has been widely used in many fields. This article introduces the performance charac...; frozenviolet Automotive Electronics

Bought an e-paper screen: I bought an e-paper screen. This thing has low power consumption and is suitable for low-power battery-powered applications. Here is the link to the information [url=http://www.waveshare.net/shop/1.54...; dql2016 NXP MCU

Imported capacitor identification: Unit: The basic unit is P, and the auxiliary units are G, M, and N. The conversion relationship is: ......; zzzzer16 Discrete Device

About DSP BIOS interrupt management: When developing applications using the DSP/BIOS kernel, users cannot modify the location of the interrupt vector table at will. The interrupt vector table will be determined by the MEM module in the D...; Jacktang DSP and ARM Processors

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components