S71PL129JC0/S71PL129JB0/S71PL129JA0
Stacked Multi-Chip Product (MCP) Flash Memory and
pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only
Simultaneous Operation, Page Mode Flash Memory with
64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM
ADVANCE
INFORMATION
Distinctive Characteristics
MCP Features
Power supply voltage of 2.7 to 3.1 volt
High performance
— 65ns (65ns Flash, 70ns pSRAM)
Package
— 8 x 11.6 x 1.2 mm 64 ball FBGA
Operating Temperature
— –25°C to +85°C (Wireless)
— –40°C to +85°C (Industrial)
Dual CE# Flash memory
General Description
The S71PL129J series is a product line of stacked Multi-Chip Product (MCP) pack-
ages and consists of:
One S29PL129J Flash memory die
One 16M, 32M, or 64M pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheets for
further details.
Flash Memory Density
128Mb
64Mb
pSRAM
Density
32Mb
16Mb
S71PL129JC0
S71PL129JB0
S71PL129JA0
Publication Number
S71PL129Jxx_00
Revision
A
Amendment
5
Issue Date
December 23, 2004
This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
Product Selector Guide
128 Mb Flash Memory
Device-Model#
S71PL129JA0-9P
S71PL129JB0-9Z
S71PL129JB0-9B
S71PL129JB0-9U
S71PL129JC0-9Z
S71PL129JC0-9U
pSRAM density
16M pSRAM
32M pSRAM
32M pSRAM
32M pSRAM
64M pSRAM
64M pSRAM
Flash Access time (ns) (p)SRAM Access time (ns) pSRAM type
65
65
65
65
65
65
70
70
70
70
70
70
Type 7
Type 7
Type 2
Type 6
Type 7
Type 6
Package
TLA064
TLA064
TLA064
TLA064
TLA064
TLA064
2
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A5_E December 23, 2004
A d v a n c e
I n f o r m a t i o n
S71PL129JC0/S71PL129JB0/S71PL129JA0
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
Write Protect (WP#) ....................................................................................... 36
Persistent Protection Bit Lock ................................................................... 37
High Voltage Sector Protection ..................................................................... 37
Figure 1. In-System Sector Protection/Sector Unprotection
Algorithms........................................................................ 38
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
128 Mb Flash Memory ..........................................................................................2
Temporary Sector Unprotect ........................................................................ 39
Figure 2. Temporary Sector Unprotect Operation ................... 39
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7
Input/Output Description . . . . . . . . . . . . . . . . . . . 8
Pin Description ......................................................................................................8
Logic Symbol ...........................................................................................................8
Secured Silicon Sector Flash Memory Region ........................................... 39
Factory-Locked Area (64 words) ..............................................................40
Customer-Lockable Area (64 words) ......................................................40
Secured Silicon Sector Protection Bits ....................................................40
Figure 3. Secured Silicon Sector Protect Verify ...................... 41
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 11
TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ............................................................................................ 11
Hardware Data Protection ..............................................................................41
Low VCC Write Inhibit .................................................................................41
Write Pulse “Glitch” Protection ................................................................ 41
Logical Inhibit ....................................................................................................41
Power-Up Write Inhibit ................................................................................ 41
S29PL129J for MCP
General Description . . . . . . . . . . . . . . . . . . . . . . . . 14
Simultaneous Read/Write Operation with Zero Latency ...................... 14
Page Mode Features ........................................................................................... 14
Standard Flash Memory Features ................................................................... 14
Common Flash Memory Interface (CFI) . . . . . . 42
Table 8. CFI Query Identification String ................................ 42
Table 9. System Interface String ......................................... 43
Table 10. Device Geometry Definition ................................... 43
Table 11. Primary Vendor-Specific Extended Query ................ 43
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 45
Reading Array Data ........................................................................................... 45
Reset Command ................................................................................................. 45
Autoselect Command Sequence ....................................................................46
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-
quence ....................................................................................................................46
Word Program Command Sequence ...........................................................46
Unlock Bypass Command Sequence ........................................................ 47
Figure 4. Program Operation ............................................... 48
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 19
Table 1. PL129J Device Bus Operations ................................ 19
Requirements for Reading Array Data ......................................................... 19
Random Read (Non-Page Read) ............................................................... 20
Page Mode Read ............................................................................................. 20
Table 2. Page Select .......................................................... 20
Simultaneous Read/Write Operation .......................................................... 20
Writing Commands/Command Sequences ................................................. 21
Accelerated Program Operation ............................................................... 21
Autoselect Functions ..................................................................................... 21
Standby Mode ........................................................................................................21
Automatic Sleep Mode ..................................................................................... 22
RESET#: Hardware Reset Pin ........................................................................ 22
Output Disable Mode ....................................................................................... 22
Table 3. S29PL129J Sector Architecture ............................... 23
Table 4. Secured Silicon Sector Addresses ............................ 29
Chip Erase Command Sequence ...................................................................48
Sector Erase Command Sequence ................................................................49
Figure 5. Erase Operation ................................................... 50
Autoselect Mode ................................................................................................ 29
Table 5. Autoselect Codes for PL129J ................................... 30
Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/
Unprotection ..................................................................... 31
Selecting a Sector Protection Mode ..............................................................32
Table 7. Sector Protection Schemes ..................................... 32
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 32
Persistent Sector Protection ...........................................................................32
Password Sector Protection ............................................................................32
WP# Hardware Protection .............................................................................32
Selecting a Sector Protection Mode ..............................................................32
Erase Suspend/Erase Resume Commands ..................................................50
Password Program Command ........................................................................ 51
Password Verify Command .............................................................................. 51
Password Protection Mode Locking Bit Program Command ............... 51
Persistent Sector Protection Mode Locking Bit Program Command 52
Secured Silicon Sector Protection Bit Program Command .................. 52
PPB Lock Bit Set Command ............................................................................ 52
DYB Write Command ...................................................................................... 52
Password Unlock Command .......................................................................... 52
PPB Program Command .................................................................................. 53
All PPB Erase Command .................................................................................. 53
DYB Write Command ...................................................................................... 53
PPB Lock Bit Set Command ............................................................................ 53
Command ............................................................................................................. 54
Command Definitions Tables ......................................................................... 54
Table 12. Memory Array Command Definitions ...................... 54
Table 13. Sector Protection Command Definitions .................. 55
Write Operation Status . . . . . . . . . . . . . . . . . . . . 56
DQ7: Data# Polling ............................................................................................ 56
Figure 6. Data# Polling Algorithm ........................................ 58
Persistent Sector Protection . . . . . . . . . . . . . . . . 33
Persistent Protection Bit (PPB) .......................................................................33
Persistent Protection Bit Lock (PPB Lock) .................................................33
Dynamic Protection Bit (DYB) .......................................................................33
Persistent Sector Protection Mode Locking Bit ........................................35
RY/BY#: Ready/Busy# ....................................................................................... 58
DQ6: Toggle Bit I ...............................................................................................58
Figure 7. Toggle Bit Algorithm ............................................. 59
Password Protection Mode . . . . . . . . . . . . . . . . . 35
Password and Password Mode Locking Bit ................................................36
64-bit Password ...................................................................................................36
DQ2: Toggle Bit II ..............................................................................................60
Reading Toggle Bits DQ6/DQ2 .....................................................................60
DQ5: Exceeded Timing Limits ........................................................................60
DQ3: Sector Erase Timer .................................................................................61
December 23, 2004 S71PL129Jxx_00_A5
3
A d v a n c e
I n f o r m a t i o n
Table 14. Write Operation Status ......................................... 61
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .62
Figure 8. Maximum Overshoot Waveforms............................. 62
Write Timings ......................................................................................................85
Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)....... 85
Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 86
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Industrial (I) Devices ..........................................................................................63
Extended (E) Devices .........................................................................................63
Supply Voltages ....................................................................................................63
Deep Power-down Timing ..............................................................................86
Figure 28. Deep Power Down Timing .................................... 86
Power-on Timing ................................................................................................86
Figure 29. Power-on Timing ................................................ 86
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 15. CMOS Compatible ................................................ 64
Provisions of Address Skew ............................................................................87
Read ....................................................................................................................87
Figure 30. Read................................................................. 87
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65
Test Conditions ...................................................................................................65
Figure 9. Test Setups......................................................... 65
Table 16. Test Specifications ............................................... 65
Write ..................................................................................................................87
Figure 31. Write ................................................................ 87
Switching Waveforms ........................................................................................65
Table 17. Key to Switching Waveforms ................................. 65
Figure 10. Input Waveforms and Measurement Levels............. 66
pSRAM Type 1
Functional Description . . . . . . . . . . . . . . . . . . . . . 88
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 88
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 94
Output Load Circuit .......................................................................................... 95
Figure 32. Output Load Circuit............................................. 95
VCC RampRate .................................................................................................. 66
Read Operations ................................................................................................ 66
Table 18. Read-Only Operations .......................................... 66
Figure 11. Read Operation Timings ....................................... 67
Figure 12. Page Read Operation Timings ............................... 67
Reset ...................................................................................................................... 68
Table 19. Hardware Reset (RESET#) .................................... 68
Figure 13. Reset Timings..................................................... 68
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 95
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 96
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 107
Read Cycle ...........................................................................................................107
Figure 33. Timing of Read Cycle
(CE# = OE# = V
IL
, WE# = ZZ# = V
IH
) .............................. 107
Figure 34. Timing Waveform of Read Cycle
(WE# = ZZ# = V
IH
)......................................................... 108
Figure 35. Timing Waveform of Page Mode Read Cycle
(WE# = ZZ# = V
IH
)......................................................... 109
Figure 36. Timing Waveform of Write Cycle
(WE# Control, ZZ# = V
IH
)................................................ 110
Figure 37. Timing Waveform of Write Cycle
(CE# Control, ZZ# = V
IH
)................................................. 110
Figure 38. Timing Waveform of Page Mode Write Cycle
(ZZ# = V
IH
) ................................................................... 111
Erase/Program Operations ............................................................................. 69
Table 20. Erase and Program Operations .............................. 69
Timing Diagrams ................................................................................................. 70
Figure 14. Program Operation Timings .................................. 70
Figure 15. Accelerated Program Timing Diagram .................... 70
Figure 16. Chip/Sector Erase Operation Timings ..................... 71
Figure 17. Back-to-back Read/Write Cycle Timings ................. 72
Figure 18. Data# Polling Timings
(During Embedded Algorithms) ............................................ 72
Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 73
Figure 20. DQ2 vs. DQ6 ...................................................... 73
Write Cycle ..........................................................................................................110
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 21. Temporary Sector Unprotect ................................. 74
Figure 21. Temporary Sector Unprotect Timing Diagram.......... 74
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 75
Controlled Erase Operations ..........................................................................76
Table 22. Alternate CE# Controlled Erase and
Program Operations ........................................................... 76
Table 23. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ............................................................. 77
Table 24. CE1#/CE2# Timing ............................................. 77
Figure 23. Timing Diagram for Alternating Between CE1# and CE2#
Control ............................................................................. 78
Table 25. Erase And Programming Performance .................... 78
Partial Array Self Refresh (PAR) .....................................................................111
Temperature Compensated Refresh (for 64Mb) .....................................112
Deep Sleep Mode ...............................................................................................112
Reduced Memory Size (for 32M and 16M) ..................................................112
Other Mode Register Settings (for 64M) ....................................................112
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 78
Figure 39. Mode Register .................................................. 113
Figure 40. Mode Register Update Timings (UB#, LB#, OE# are
Don’t Care)..................................................................... 113
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 114
Figure 42. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M)........................................................... 114
pSRAM Type 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Functional Description . . . . . . . . . . . . . . . . . . . . . 80
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 80
AC Characteristics and Operating Conditions . 81
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 82
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .83
Read Timings ........................................................................................................83
Figure 24. Read Cycle ......................................................... 83
Figure 25. Page Read Cycle (8 Words Access) ........................ 84
Type 2 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Information . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . .
118
118
118
119
119
Power Up ..............................................................................................................119
Figure 43. Power Up 1 (CS1# Controlled) ........................... 119
Figure 44. Power Up 2 (CS2 Controlled).............................. 119
Functional Description . . . . . . . . . . . . . . . . . . . . 120
Absolute Maximum Ratings . . . . . . . . . . . . . . . 120
DC Recommended Operating Conditions . . . . 120
S71PL129Jxx_00_A5 December 23, 2004
4
A d v a n c e
I n f o r m a t i o n
DC and Operating Characteristics . . . . . . . . . . . 121
Common ............................................................................................................... 121
16M pSRAM ......................................................................................................... 122
32M pSRAM ........................................................................................................ 122
64M pSRAM ........................................................................................................ 123
128M pSRAM ....................................................................................................... 123
Power Down Parameters ............................................................................... 137
Other Timing Parameters ............................................................................... 137
AC Test Conditions .........................................................................................138
AC Measurement Output Load Circuits ...................................................138
Figure 53. AC Output Load Circuit – 16 Mb.......................... 138
Figure 54. AC Output Load Circuit – 32 Mb and 64 Mb .......... 138
AC Operating Conditions . . . . . . . . . . . . . . . . . 124
Test Conditions (Test Load and Test Input/Output Reference) ....... 124
Figure 45. Output Load ..................................................... 124
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139
Read Timings .......................................................................................................139
Figure 55. Read Timing #1 (Basic Timing) .......................... 139
Figure 56. Read Timing #2 (OE# Address Access................. 139
Figure 57. Read Timing #3 (LB#/UB# Byte Access) ............. 140
Figure 58. Read Timing #4 (Page Address Access after CE1#
Control Access for 32M and 64M Only) ............................... 140
Figure 59. Read Timing #5 (Random and Page Address Access for
32M and 64M Only) ......................................................... 141
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 126
Read Timings ...................................................................................................... 126
Figure 46. Timing Waveform of Read Cycle(1)...................... 126
Figure 47. Timing Waveform of Read Cycle(2)...................... 126
Figure 48. Timing Waveform of Page Cycle (Page Mode Only) 127
Write Timings .................................................................................................... 127
Figure 49. Write Cycle #1 (WE# Controlled) ........................
Figure 50. Write Cycle #2 (CS1# Controlled) .......................
Figure 51. Timing Waveform of Write Cycle(3)
(CS2 Controlled) ..............................................................
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB#
Controlled) ......................................................................
127
128
128
129
Write Timings ......................................................................................................141
Figure 60. Write Timing #1 (Basic Timing) ..........................
Figure 61. Write Timing #2 (WE# Control)..........................
Figure 62. Write Timing #3-1
(WE#/LB#/UB# Byte Write Control) ..................................
Figure 63. Write Timing #3-3
(WE#/LB#/UB# Byte Write Control) ..................................
Figure 64. Write Timing #3-4
(WE#/LB#/UB# Byte Write Control) ..................................
Figure 65. Read/Write Timing #1-1 (CE1# Control) .............
Figure 66. Read / Write Timing #1-2
(CE1#/WE#/OE# Control) ................................................
Figure 67. Read / Write Timing #2 (OE#, WE# Control) .......
Figure 68. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control) ........................................
Figure 69. Power-up Timing #1 .........................................
Figure 70. Power-up Timing #2 .........................................
Figure 71. Power Down Entry and Exit Timing .....................
Figure 72. Standby Entry Timing after Read or Write............
Figure 73. Power Down Program Timing (for 32M/64M Only).
141
142
142
143
143
144
144
145
145
146
146
146
147
147
pSRAM Type 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Functional Description . . . . . . . . . . . . . . . . . . . . . 131
Power Down (for 32M, 64M Only) . . . . . . . . . . . . 131
Power Down ....................................................................................................... 131
Power Down Program Sequence ................................................................. 132
Address Key ....................................................................................................... 132
Read/Write Timings ..........................................................................................144
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 133
Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 133
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 134
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 135
Read Operation ..................................................................................................135
Write Operation ............................................................................................... 136
Revision Summary
December 23, 2004 S71PL129Jxx_00_A5
5
FPGA/CPLD
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