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S3CB018: DescriptionThe S3CB018/FB018 single-chip CMOS microcontroller; File Size162KB，33 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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S3CB018 Overview

The S3CB018/FB018 single-chip CMOS microcontroller

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S3CB018/FB018

PRODUCT OVERVIEW

CALMRISC OVERVIEW

The S3CB018/FB018 single-chip CMOS microcontroller is designed for high performance using Samsung’ s

newest 8-bit CPU core, CalmRISC.

CalmRISC is an 8-bit low power RISC microcontroller. Its basic architecture follows Harvard style, that is, it has

separate program memory and data memory. Both instruction and data can be fetched simultaneously without

causing a stall, using separate paths for memory access. Represented below is the top block diagram of the

CalmRISC microcontroller.

1-1

PRODUCT OVERVIEW

S3CB018/FB018

The CalmRISC building blocks consist of:

— An 8-bit ALU

— 16 general purpose registers (GPR)

— 11 special purpose registers (SPR)

— 16-level hardware stack

— Program memory address generation unit

— Data memory address generation unit

16 GPR’ s are grouped into four banks (Bank0 to Bank3) and each bank has four 8-bit registers (R0, R1, R2, and

R3). SPR’ s, designed for special purposes, include status registers, link registers for branch-link instructions, and

data memory index registers. The data memory address generation unit provides the data memory address

(denoted as

DA[15:0]

in the top block diagram) for a data memory access instruction. Data memory contents are

accessed through

DI[7:0]

for read operations and

DO[7:0]

for write operations. The program memory address

generation unit contains a program counter, PC[19:0], and supplies the program memory address through

PA[19:0]

and fetches the corresponding instruction through

PD[15:0]

as the result of the program memory access.

CalmRISC has a 16-level hardware stack for low power stack operations as well as a temporary storage area.

CalmRISC has a 3-stage pipeline as described below:

Instruction Fetch

(IF)

Instruction Decode/

Data Memory Access

(ID/MEM)

Execution/Writeback

(EXE/WB)

Figure 1-2. CalmRISC Pipeline Diagram

As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data

memory where

is a GPR, can be one operand of an ALU instruction as shown below:

The first stage (or cycle) is Instruction Fetch stage (IF for short), where the instruction pointed to by the program

counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is Instruction Decode and

Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and data

memory access is performed, if necessary. The final stage is Execute and Write-back stage (EXE/WB), where the

required ALU operation is executed and the result is written back into the destination registers.

Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction

is completely finished, but is performed immediately after the current instruction fetch is done. The pipeline stream

of instructions is illustrated in the following diagram.

1-4

S3CB018 Related Products

	S3CB018	S3FB018
Description	The S3CB018/FB018 single-chip CMOS microcontroller	The S3CB018/FB018 single-chip CMOS microcontroller

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