BLF8G24L-200P;
BLF8G24LS-200P
Power LDMOS transistor
Rev. 3 — 12 July 2013
Product data sheet
1. Product profile
1.1 General description
200 W LDMOS power transistor for base station applications at frequencies from
2300 MHz to 2400 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
C in a common source class-AB production test circuit.
Test signal
1-carrier W-CDMA
[1]
f
(MHz)
2300 to 2400
I
Dq
(mA)
1740
V
DS
(V)
28
P
L(AV)
(W)
60
G
p
(dB)
17.2
D
(%)
32
ACPR
5M
(dBc)
37
[1]
Test signal: 3GPP test model 1; 64 DPCH; PAR = 7.2 dB at 0.01 % probability on CCDF.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low R
th
providing excellent thermal stability
Designed for broadband operation (2300 MHz to 2400 MHz)
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent pre-distortability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 2300 MHz to
2400 MHz frequency range
NXP Semiconductors
BLF8G24L-200P; BLF8G24LS-200P
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
4
5
Pinning
Description
drain1
drain2
gate1
gate2
source
[1]
Simplified outline
Graphic symbol
BLF8G24L-200P (SOT539A)
1
2
5
3
3
4
4
5
1
2
sym117
BLF8G24LS-200P (SOT539B)
1
2
3
4
5
drain1
drain2
gate1
gate2
source
[1]
1
2
5
3
1
3
4
5
4
2
sym117
[1]
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Package
Name Description
BLF8G24L-200P
BLF8G24LS-200P
-
-
flanged balanced ceramic package; 2 mounting holes;
4 leads
earless flanged balanced ceramic package; 4 leads
Version
SOT539A
SOT539B
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
T
stg
T
j
T
case
[1]
Parameter
drain-source voltage
gate-source voltage
storage temperature
junction temperature
case temperature
Conditions
Min
-
0.5
65
-
[1]
Max
65
+13
+150
200
150
Unit
V
V
C
C
C
-
Continuous use at maximum temperature will affect the MTTF.
BLF8G24L-200P_LS-200P
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 12 July 2013
2 of 13
NXP Semiconductors
BLF8G24L-200P; BLF8G24LS-200P
Power LDMOS transistor
5. Thermal characteristics
Table 5.
Symbol
R
th(j-c)
Thermal characteristics
Parameter
thermal resistance from junction to case
Conditions
T
case
= 80
C;
P
L
= 60 W
Typ
Unit
0.217 K/W
6. Characteristics
Table 6.
DC characteristics
T
j
= 25
C per section, unless otherwise specified.
Symbol Parameter
V
GS(th)
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
Conditions
V
DS
= 10 V;
I
D
= 100 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 5.1 A
Min
65
1.5
-
-
-
-
-
Typ
-
1.9
-
26.8
-
1.2
0.1
Max
-
2.3
2.8
-
280
-
-
Unit
V
V
A
A
nA
S
V
(BR)DSS
drain-source breakdown voltage V
GS
= 0 V; I
D
= 1 mA
drain-source on-state resistance V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 5.04 A
Table 7.
RF characteristics
Test signal: 1-carrier W-CDMA, PAR = 7.2 dB at 0.01 % probability on the CCDF,
3GPP test model 1; 64 DPCH; f
1
= 2300 MHz; f
2
= 2400 MHz; RF performance at V
DS
= 28 V;
I
Dq
= 1740 mA; T
case
= 25
C; unless otherwise specified; in a class-AB production test circuit.
Symbol
P
L(AV)
G
p
RL
in
D
ACPR
5M
Parameter
average output power
power gain
input return loss
drain efficiency
adjacent channel power ratio (5 MHz)
Conditions
Min
-
15.8
-
27
-
Typ Max
60
11
32
-
8
-
17.2 -
Unit
W
dB
dB
%
dBc
37 33
7. Test information
7.1 Ruggedness in class-AB operation
The BLF8G24L-200P and BLF8G24LS-200P are capable of withstanding a load
mismatch corresponding to VSWR = 10 : 1 through all phases under the following
conditions: V
DS
= 28 V; I
Dq
= 1740 mA; P
L
= 200 W (CW); f = 2300 MHz.
BLF8G24L-200P_LS-200P
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 12 July 2013
3 of 13
NXP Semiconductors
BLF8G24L-200P; BLF8G24LS-200P
Power LDMOS transistor
7.2 Impedance information
Table 8.
Typical impedance
Measured load-pull data half section; V
DS
= 28 V; I
Dq
= 860 mA; typical values unless otherwise
specified.
f
(MHz)
2300
2400
[1]
Z
S
and Z
L
defined in
Figure 1.
Z
S[1]
()
4.24
j6.5
7.47
j6.07
Z
L[1]
()
1.5
j5.4
1.5
j5.5
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
7.3 Test circuit
See
Table 9
for list of components.
Fig 2.
Component layout
BLF8G24L-200P_LS-200P
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 12 July 2013
4 of 13
NXP Semiconductors
BLF8G24L-200P; BLF8G24LS-200P
Power LDMOS transistor
Table 9.
List of components
See
Figure 2
for component layout.
The used PCB material is Rogers RO4350B with a thickness of 0.76 mm.
Component
C1, C2, C9, C10
C3, C4, C6, C7
C5, C8
C11, C12, C13, C14
C15, C16
R1, R2
[1]
[2]
[3]
Description
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
electrolytic capacitor
chip resistor
Value
6.8
F
1
F
33 pF
0.1
F
1000
F;
50 V
5.1
[3]
[1]
[2]
[1]
[2]
Remarks
American Technical Ceramics type 100B or capacitor of same quality.
Murata or capacitor of same quality.
Vishay Dale or resistor of same quality.
7.4 Graphical data
7.4.1 1-Tone CW
V
DS
= 28 V; I
Dq
= 1740 mA.
(1) f = 2300 MHz
(2) f = 2400 MHz
Fig 3.
Power gain and drain efficiency as function of load power; typical values
BLF8G24L-200P_LS-200P
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 12 July 2013
5 of 13
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