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5962F9565202VCX

Description
AC SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14
Categorylogic    logic   
File Size269KB,21 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
Download Datasheet Parametric View All

5962F9565202VCX Overview

AC SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14

5962F9565202VCX Parametric

Parameter NameAttribute value
Objectid1536263430
Parts packaging codeDIP
package instructionDIP,
Contacts14
Reach Compliance Codeunknown
seriesAC
JESD-30 codeR-CDIP-T14
Logic integrated circuit typeNAND GATE
Number of functions3
Number of entries3
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)16 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal locationDUAL
total dose300k Rad(Si) V
REVISIONS
LTR
A
B
C
D
DESCRIPTION
Changes in accordance with NOR 5962-R305-97.
Changes in accordance with NOR 5962-R030-99.
Update boilerplate to MIL-PRF-38535 and updated appendix A. Editorial
changes throughout. – tmh
Update radiation features in section 1.5, table IB SEP test limits, and
paragraphs 4.4.4.1 – 4.4.4.4. Update boilerplate paragraphs to the current
MIL-PRF-38535 requirements. - LTG
Update radiation features in section 1.5 and add SEP table IB. Update the
boilerplate paragraphs to current requirements as specified in
MIL-PRF-38535. - MAA
DATE (YR-MO-DA)
97-10-22
99-02-19
00-07-20
10-03-25
APPROVED
Monica L. Poelking
Monica L. Poelking
Monica L. Poelking
Thomas M. Hess
E
16-12-21
Muhammad Akbar
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
E
15
E
16
E
17
E
18
REV
SHEET
PREPARED BY
Joseph A. Kerby
E
19
E
20
E
1
E
2
E
3
E
4
E
5
E
6
E
7
E
8
E
9
E
10
E
11
E
12
E
13
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14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
CHECKED BY
Thanh V. Nguyen
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
95-12-20
REVISION LEVEL
E
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED, ADVANCED CMOS, TRIPLE THREE-
INPUT NAND GATE, MONOLITHIC SILICON
SIZE
A
CAGE CODE
AMSC N/A
67268
5962-95652
SHEET 1 OF 20
DSCC FORM 2233
APR 97
5962-E454-16

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