Not recommended for new designs –
Please use 24LCS21A.
24LC21
1K 2.5V Dual Mode I
2
C
™
Serial EEPROM
Features:
• Single supply with operation down to 2.5V
• Completely implements DDC1
™
/DDC2
™
interface
for monitor identification
• Low-power CMOS technology:
- 1 mA active current typical
- 10
µA
standby current typical at 5.5V
• 2-wire serial interface bus, I
2
C
™
compatible
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available
• 1,000,000 erase/write cycles ensured
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
Commercial (C):
0°C to +70°C
Industrial (I):
-40°C to +85°C
Package Types
PDIP
NC
NC
NC
V
SS
1
2
3
4
24LC21
8
7
6
5
V
CC
V
CLK
SCL
SDA
SOIC
1
2
3
4
24LC21
8
7
5
5
NC
NC
NC
V
SS
V
CC
V
CLK
SCL
SDA
Description:
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed
for use in applications requiring storage and serial
transmission of configuration and control information.
Two modes of operation have been implemented:
Transmit-only mode and Bidirectional mode. Upon
power-up, the device will be in the Transmit-only mode,
sending a serial bit stream of the entire memory array
contents, clocked by the V
CLK
pin. A valid high-to-low
transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array. The 24LC21 is available
in a standard 8-pin PDIP and SOIC package, in both
commercial and industrial temperature ranges.
Block Diagram
V
CLK
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
SDA SCL
YDEC
V
CC
V
SS
Sense Amp
R/W Control
I
2
C is a trademark of Philips Corporation.
DDC is a trademark of the Video Electronics Standards Association.
2004 Microchip Technology Inc.
DS21095J-page 1
24LC21
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
........................................................................................................ -0.6V to V
CC
+ 1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
V
CC
= +2.5V to 5.5V
Commercial (C): T
A
= 0°C to +70°C
Industrial
(I): T
A
= -40°C to +85°C
Symbol
V
IH
V
IL
Min
.7 V
CC
—
Max
—
.3 V
CC
Units
V
V
—
—
V
CC
≥
2.7V
(Note 1)
V
CC
< 2.7V
(Note 1)
(Note 1)
I
OL
= 3 mA, V
CC
= 2.5V
(Note 1)
I
OL
= 6 mA, V
CC
= 2.5V
V
IN
= .1V to V
CC
V
OUT
= .1V to V
CC
V
CC
= 5.0V
(Note1),
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
(Note 2)
Conditions
DC CHARACTERISTICS
Parameter
SCL and SDA pins:
High-level input voltage
Low-level input voltage
Input levels on V
CLK
pin:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt Trigger inputs
Low-level output voltage
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
V
IH
V
IL
V
HYS
V
OL1
V
OL2
I
LI
I
LO
C
IN
, C
OUT
I
CC
Write
I
CC
Read
I
CCS
2.0
—
.05 V
CC
—
—
-10
-10
—
—
—
—
—
.8
.2 V
CC
—
.4
.6
10
10
10
3
1
30
100
V
V
V
V
V
µA
µA
pF
mA
mA
µA
µA
Note 1:
2:
This parameter is periodically sampled and not 100% tested.
V
LCK
must be grounded.
DS21095J-page 2
2004 Microchip Technology Inc.
24LC21
TABLE 1-2:
AC CHARACTERISTICS
Standard Mode
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
Symbol
Min
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max
100
—
—
1000
300
—
—
—
—
—
3500
—
Vcc= 4.5 - 5.5V
Fast Mode
Min
—
600
1300
—
—
600
600
0
100
600
—
1300
Max
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
Start condition
(Note 2)
—
—
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1),
C
B
≤
100 pF
(Note 3)
Byte or Page mode
—
—
—
—
—
25°C, V
CC
= 5.0V, Block
mode
(Note 4)
Units
Remarks
T
OF
Output fall time from V
IH
min. to V
IL
max.
Input filter spike suppres-
T
SP
sion (SDA and SCL pins)
Write cycle time
T
WR
Transmit-only Mode Parameters
Output valid from V
CLK
T
VAA
V
CLK
high time
T
VHIGH
V
CLK
low time
T
VLOW
Mode transition time
T
VHZ
Transmit-only power-up
T
VPU
time
Endurance
—
Note 1:
2:
3:
4:
—
—
—
—
4000
4700
—
0
1M
250
50
10
2000
—
—
500
—
—
20 + .1
C
B
—
—
—
600
1300
—
0
1M
250
50
10
1000
—
—
500
—
—
ns
ns
ms
ns
ns
ns
ns
ns
cycles
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance
™
Model which can be obtained from Microchip’s web site
at: www.microchip.com
2004 Microchip Technology Inc.
DS21095J-page 3
24LC21
2.0
FUNCTIONAL DESCRIPTION
The 24LC21 operates in two modes, the Transmit-only
mode and the Bidirectional mode. There is a separate
two wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-only mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
V
CLK
pin. The device will remain in this mode until a
valid high-to-low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bidirectional mode. The only
way to switch the device back to the Transmit-only
mode is to remove power from the device.
mitted on the SDA pin in 8-bit bytes, each followed by
a ninth, null bit (see Figure 2-1). The clock source for
the Transmit-only mode is provided on the V
CLK
pin,
and a data bit is output on the rising edge on this pin.
The eight bits in each byte are transmitted Most Signif-
icant bit first. Each byte within the memory array will be
output in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bidirectional mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-only mode.
2.2
Initialization Procedure
2.1
Transmit-only Mode
The device will power-up in the Transmit-only mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see Initial-
ization Procedure, below). In this mode, data is trans-
After V
CC
has stabilized, the device will be in the Trans-
mit-only mode. Nine clock cycles on the V
CLK
pin must
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit of a byte. The
device will power-up at an indeterminate byte address.
(Figure 2-2).
FIGURE 2-1:
TRANSMIT-ONLY MODE
SCL
T
VAA
T
VAA
SDA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB)
Bit 7
V
CLK
T
VHIGH
T
VLOW
FIGURE 2-2:
DEVICE INITIALIZATION
V
CC
SCL
T
VAA
T
VAA
SDA
High-impedance for 9 clock cycles
T
VPU
Bit 8
Bit 7
V
CLK
1
2
8
9
10
11
DS21095J-page 4
2004 Microchip Technology Inc.
24LC21
3.0
BIDIRECTIONAL MODE
3.1
The 24LC21 can be switched into the Bidirectional
mode (see Figure 3-1) by applying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the V
CLK
input is disregarded, with the exception
that a logic high level is required to enable write capa-
bility. This mode supports a two wire bidirectional data
transmission protocol. In this protocol, a device that
sends data on the bus is defined to be the transmitter,
and a device that receives data from the bus is defined
to be the receiver. The bus must be controlled by a
master device that generates the Bidirectional mode
clock (SCL), controls access to the bus and generates
the Start and Stop conditions, while the 24LC21 acts as
the slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
Bidirectional Mode Bus
Characteristics
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-2).
3.1.1
BUS NOT BUSY (A)
Both data and clock lines remain high.
3.1.2
START DATA TRANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3
STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 3-1:
SCL
MODE TRANSITION
Transmit-only mode
Bidirectional mode
T
VHZ
SDA
V
CLK
FIGURE 3-2:
SCL
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
2004 Microchip Technology Inc.
DS21095J-page 5
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