P3PSL450A
Low Voltage, Timing-Safe]
Peak EMI Reduction IC
Functional Description
P3PSL450A/AH is a versatile low voltage peak EMI reduction IC
based on Timing−Safe technology. P3PSL450A/AH accepts one input
from an external reference, and locks on to it delivering a 1x
Timing−Safe output clock. P3PSL450A/AH has a Frequency
Selection (FS) control that facilitates selecting one of the two
frequency ranges within the operating frequency range. Refer
frequency Selection table.
The device has an SSEXTR pin to select
different deviations depending upon the value of an external resistor
connected at this pin to GND. P3PSL450A/AH has an MR pin for
selecting one of the two Modulation Rates. PD# provides the Power
Down option.
P3PSL450A is a Low drive part and P3PSL450AH is a High drive
part. Refer to
DC/AC Electrical characteristic
table.
P3PSL450A/AH operates over a supply voltage range of 1.8 V
$
0.2 V, and is available in an 8 Pin WDFN (2 mm x 2 mm) Package.
General Features
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MARKING
DIAGRAM
1
WDFN8
CASE 511AQ
1
XX MG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Device
•
•
•
•
•
•
•
•
•
•
PIN CONFIGURATION
CLKIN 1
FS 2
PD# 3
GND 4
8 VDD
7 SSEXTR
6 MR
5 ModOUT
1x, LVCMOS Timing−Safe Peak EMI Reduction
Input Clock Frequency: 15 MHz
−
60 MHz
Output Clock Frequency (Timing−Safe): 15 MHz
−
60 MHz
Analog Frequency Deviation Selection
Two different Modulation Rate Selection Option
Power Down option for Power Save
Low and High Drive Parts
Supply Voltage: 1.8 V
$
0.2 V
8 Pin WDFN (2 mm X 2 mm) Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Application
•
P3PSL450A/AH is targeted for use in consumer electronic
MR
applications like mobile phones, Camera modules, MFP and DPF
VDD
SSEXTR
CLKIN
PLL
ModOUT
(Timing−Safe)
PD#
GND
FS
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2010
July, 2010
−
Rev. 1
1
Publication Order Number:
P3PSL450A/D
P3PSL450A
Table 1. PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
Pin Name
CLKIN
FS
PD#
GND
ModOUT
MR
SSEXTR
VDD
Type
I
I
I
P
O
I
I
P
External reference Clock input.
Frequency Select. Has an internal pull−down resistor. see
Frequency Selection table
Power Down. Pull LOW to enable Power Down. Pull HIGH to disable power down.
Output Clock will be LOW when power down is enabled. Has an internal pull−up resistor
Ground
Buffered modulated Timing−Safe clock output
Modulation Rate Select. When LOW selects Low Modulation Rate. Selects High
Modulation Rate when pulled HIGH. Has an internal pull−up resistor.
Analog Frequency Deviation Selection through external resistor to GND.
1.8 V Supply Voltage
Description
Table 2. FREQUENCY SELECTION TABLE
FS
0
1
Frequency (MHz)
15−30
30−60
Table 3. ABSOLUTE MAXIMUM RATING
Parameter
Supply Voltage to Ground Potential
DC Input Voltage(CLKIN)
DC Input Voltage (Except CLKIN)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22−A114−B)
Min
−0.3
−0.3
−0.3
−65
Max
+2.7
+2.7
V
DD
+ 0.3
+150
260
150
2000
Unit
V
V
V
°C
°C
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. OPERATING CONDITIONS
Symbol
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature
Load Capacitance
Input Capacitance
Parameter
Min
1.6
−20
Max
2
+85
15
7
Unit
V
°C
pF
pF
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P3PSL450A
Table 5. DC ELECTRICAL CHARACTERISTICS FOR V
DD
= 1.8 V
$
0.2 V
Symbol
VDD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
CC
I
DD
Parameter
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Output HIGH Voltage
V
IN
= V
DD
V
IN
= 0 V
I
OH
=
−8
mA (P3PSL450A)
I
OH
=
−16
mA (P3PSL450AH)
Output LOW Voltage
I
OL
= 8 mA (P3PSL450A)
I
OL
= 16 mA (P3PSL450AH)
Static Supply Current
Dynamic Supply Current
CLKIN & PD# pins pulled to GND
Unloaded
Output
FS = 0, @ 15 MHz
FS = 0, @ 30 MHz
FS = 1, @ 30 MHz
FS = 1, @ 60 MHz
Z
o
Output Impedance
P3PSL450A
P3PSL450AH
1.7
3.0
2.6
4.3
23
17
10
2.2
3.7
3.7
6.4
W
mA
mA
0.25 * V
DD
V
0.75 * V
DD
Test Conditions
Min
1.6
0.65 * V
DD
0.35 * V
DD
5
5
Typ
1.8
Max
2
Unit
V
V
V
mA
mA
V
Table 6. AC ELECTRICAL CHARACTERISTICS FOR V
DD
= 1.8 V
$
0.2 V
Parameter
Input Frequency
Test Conditions
FS = 0
FS = 1
ModOUT
FS = 0
FS = 1
Duty Cycle
(Notes 1 and 2)
Rise Time
(Notes 1 and 2)
Fall Time
(Notes 1 and 2)
Cycle−to−Cycle Jitter
(Note 2)
Measured at V
DD
/ 2
Measured between 20% to
80%
Measured between 80% to
20%
Unloaded output with
SSEXTR pin OPEN
P3PSL450A
P3PSL450AH
P3PSL450A
P3PSL450AH
FS = 0
15 MHz
24 MHz
30 MHz
FS = 1
30 MHz
60 MHz
PLL Lock Time
2
Stable power supply, valid clock presented on CLKIN pin,
PD# toggled from Low to High
Min
15
30
15
30
45
50
1.3
1
1.3
1
$150
$100
$80
$150
$100
Typ
Max
30
60
30
60
55
2.1
1.7
2.1
1.7
$250
$150
$150
$250
$150
1
ms
ps
ns
%
ns
Unit
MHz
1. All parameters are specified with 15 pF loaded output.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
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3
P3PSL450A
SWITCHING WAVEFORMS
t
1
t
2
V
DD
/2
OUTPUT
V
DD
/2
V
DD
/2
Figure 2. Duty Cycle Timing
80%
20%
80%
20%
OUTPUT
t
3
t
4
Figure 3. Output Rise/Fall Time
Input
T
SKEW
Timing−Safe Output
T
SKEW/2
T
SKEW
represents input−output skew when spread spectrum is ON
For example, T
SKEW/2
=
$0.20
* T for an Input clock of 24 MHz, translates in to
(1/24 MHz) * 0.20 = 8.33 ns
Input
ModOUT with SSOFF
Figure 5. Typical Example of Timing−Safe Waveform
Î Î Î Î Î Î ÎÎÎ
Î Î Î Î Î Î ÎÎÎ
Î Î Î Î Î Î ÎÎÎ
T
SKEW/2
One clock cycle (T)
Figure 4. Input−Output Skew
Input
Timing-Safe ModOUT
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4
P3PSL450A
DEVIATION VERSUS SSEXTR RESISTANCE CHARTS
3.0
2.5
DEVIATION ($%)
2.0
1.5
1.0
0.5
0.0
3.0
2.5
DEVIATION ($%)
2.0
1.5
1.0
0.5
0.0
0
FS = 0,
MR = 0
FS = 0,
MR = 1
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 6. Deviation vs SSEXTR Chart
(CLKIN = 15 MHz)
3
2.5
DEVIATION ($%)
2
1.5
1
0.5
0
FS = 0,
MR = 0
DEVIATION ($%)
3
2.5
2
1.5
1
0.5
0
0
Figure 7. Deviation vs SSEXTR Chart
(CLKIN = 15 MHz)
FS = 0,
MR = 1
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 8. Deviation vs SSEXTR Chart
(CLKIN = 24 MHz)
2.5
2.0
DEVIATION ($%)
DEVIATION ($%)
1.0
1.5
1.0
0.5
0.0
0.0
0
1.5
Figure 9. Deviation vs SSEXTR Chart
(CLKIN = 24 MHz)
FS = 0,
MR = 0
FS = 0,
MR = 1
0.5
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 10. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
Figure 11. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
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