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5962-8959818MXX

Description
Standard SRAM, 128KX8, 45ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
Categorystorage    storage   
File Size812KB,103 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

5962-8959818MXX Overview

Standard SRAM, 128KX8, 45ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

5962-8959818MXX Parametric

Parameter NameAttribute value
Objectid1820272857
Parts packaging codeDIP
package instructionDIP,
Contacts32
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time45 ns
JESD-30 codeR-CDIP-T32
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal locationDUAL
width10.16 mm
REVISIONS
LTR
J
K
L
DESCRIPTION
Add device types 42, 43, 44, 45, and 46. Editorial changes to pages
1, 3, 7-15. Update boilerplate. ksr
Added provisions to accommodate radiation-hardened devices.
Added device type 47 to drawing. glg
Corrected case outline 8 Figure 1 to show correct numbering of
terminals. Corrected Figure 2 Terminal connections. Corrected the
case outline Y Figure 1 to show the proper distance of E and E1.
Added note to Case outline Y Figure 1, to allow for bottom brazed
package as an alternative style to the side brazed package . Update
boilerplate. Editorial changes throughout. ksr
Changed the minimum value for the Q dimension on package T from
0.026 to 0.020 and removed footnote 12. Editorial changes
throughout.. ksr
Added device type 48 to drawing. ksr
Corrected typo on Figure 4 (Read Cycle). ksr
Vendor requested change in capacitance in Table I for devices 39
and 40 from 5 pF to 8 pF. ksr
Vendor added RHA device type 49. Updated and re-sequenced
footnotes in Table I. Reformatted Appendixes. Update drawing to
current MIL-PRF-38535 requirements. - llb
DATE (YR-MO-DA)
98-03-03
00-03-01
00-12-08
APPROVED
Raymond Monnin
Raymond Monnin
Raymond Monnin
M
02-12-19
Raymond Monnin
N
P
R
T
03-08-12
05-08-16
06-02-13
14-06-25
Raymond Monnin
Raymond Monnin
Raymond Monnin
Charles F. Saffle
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
T
35
T
15
T
36
T
16
T
37
T
17
T
38
T
18
REV
T
39
T
19
T
40
T
20
T
41
T
21
T
1
T
42
T
22
T
2
T
43
T
23
T
3
T
44
T
24
T
4
T
45
T
25
T
5
T
46
T
26
T
6
T
47
T
27
T
7
T
48
T
28
T
8
T
49
T
29
T
9
T
50
T
30
T
10
T
51
T
31
T
11
T
52
T
32
T
12
T
53
T
33
T
13
T
54
T
34
T
14
SHEET
PREPARED BY
Kenneth S. Rice
CHECKED BY
Raymond Monnin
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
APPROVED BY
Michael A. Frye
DRAWING APPROVAL DATE
89-04-21
REVISION LEVEL
T
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, 128K X 8 STATIC RANDOM
ACCESS MEMORY (SRAM) LOW POWER,
MONOLITHIC SILICON
SIZE
A
SHEET
CAGE CODE
67268
1 OF
54
5962-89598
5962-E258-13
DSCC FORM 2233
APR 97
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