CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
PARAMETER
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
Zero Gate Voltage Drain Current
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
TEST CONDITIONS
I
D
= 250µA, V
GS
= 0V
V
GS
= V
DS
, I
D
= 1mA (Figure 9)
T
J
= 25
o
C, V
DS
= 500V, V
GS
= 0V
T
J
= 125
o
C, V
DS
= 500V, V
GS
= 0V
MIN
500
2.1
-
-
-
-
1.5
-
-
-
-
V
DS
= 25V, V
GS
= 0V, f = 1MHz (Figure 10)
-
-
-
TYP
-
3
20
100
10
1.6
2.5
30
40
110
50
1500
110
40
≤
1.67
≤
75
MAX
-
4
250
1000
100
2.000
-
45
60
140
65
2000
170
70
UNITS
V
V
µA
µA
nA
Ω
S
ns
ns
ns
ns
pF
pF
pF
o
C/W
o
C/W
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Forward Transconductance (Note 2)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
I
GSS
r
DS(ON)
gfs
t
d(ON)
t
r
t
d(OFF)
t
f
C
ISS
C
OSS
C
RSS
R
θJC
R
θJA
V
GS
= 20V, V
DS
= 0V
I
D
= 2.5A, V
GS
= 10V (Figure 8)
V
DS
= 25V, I
D
= 2.5A (Figure 11)
V
CC
= 30V, I
D
≈
2.5A, V
GS
= 10V, R
GS
= 50Ω,
R
L
= 10Ω. (Figures 16, 17)
Source to Drain Diode Specifications
PARAMETER
Continuous Source to Drain Current
Pulsed Source to Drain Current
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovery Charge
NOTES:
2. Pulse Test: Pulse width
≤
300µs, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
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FPGA/CPLD
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