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S29AL008D
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
Data Sheet
Distinctive Characteristics
Architectural Advantage
Single power supply operation
— 2.7 to 3.6 volt read and write operations for battery-
powered applications
Performance Characteristics
High performance
— Access times as fast as 55 ns
— Extended temperature range (-40°C to +125°C)
Manufactured on 200nm process technology
— Compatible with 0.32 µm and 230nm Am29LV160
devices
Ultra low power consumption (typical values
at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen
64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and fifteen
32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
— A hardware method of locking a sector to prevent
any program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Cycling endurance: 1,000,000 cycles per
sector typical
Data retention: 20 years typical
— Reliable operation for the life of the system
Package option
48-ball FBGA
48-pin TSOP
44-pin SO
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Software Features
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
Top or bottom boot block configurations
available
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Hardware Features
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
Publication Number
S29AL008D_00
Revision
A
Amendment
3
Issue Date
June 16, 2005
“This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products
to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical
or specification corrections, or modifications to the valid combinations offered may occur.”
D a t a
S h e e t
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, in-
cluding development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to high-
light their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a doc-
ument with this designation is likely to change, and in some cases, development on the product
may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa-
tion content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the prod-
uct life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon Prelimi-
nary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V
IO
range. Changes
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
2
S29AL008D
S29AL008D_00A3 June 16, 2005
D a t a
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General Description
The S29AL008D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576
bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and
48-pin TSOP packages. For more information, refer to publication number 21536.
The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data ap-
pears on DQ7–DQ0. This device requires only a single, 3.0 volt V
CC
supply to
perform read, program, and erase operations. A standard EPROM programmer
can also be used to program and erase the device.
This device is manufactured using Spansion’s 200nm process technology, and of-
fers all the features and benefits of the Am29LV800B, which was manufactured
using 0.32 µm process technology.
The standard device offers access times of 70, 90, and 120 ns, allowing high
speed microprocessors to operate without wait states. To eliminate bus conten-
tion the device contains separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
The device requires only a
single 3.0 volt power supply
for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-
supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an in-
ternal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the
Embedded Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the
erase operation. During erase, the device automatically times the erase pulse
widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog-
gle)
status bits.
After a program or erase cycle is completed, the device is ready
to read array data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The
hardware sector
protection
feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
June 16, 2005 S29AL008D_00A3
S29AL008D
3
D a t a
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The
Erase Suspend
feature enables the user to put erase on hold for any period
of time to read data from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the
internal state machine to reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also reset the device, enabling
the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a
specified amount of time, the device enters the
automatic sleep mode.
The
system can also place the device into the
standby mode.
Power consumption is
greatly reduced in both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing ex-
perience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simulta-
neously via Fowler-Nordheim tunneling. The data is programmed using hot
electron injection.
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S29AL008D
S29AL008D_00A3 June 16, 2005
D a t a
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Table Of Contents
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . 8
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7. Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . 33
Figure 8. Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Typical I
CC1
vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 11
Table 1. S29AL008D Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .11
Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . 11
Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . 12
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. S29AL008D Top Boot Block Sector Addresses . . . . . . . . . . . 14
Table 3. S29AL008D Bottom Boot Block Sector Addresses . . . . . . . . 15
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. S29AL008D Autoselect Codes (High Voltage Method) . . . . . 16
Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 1. Temporary Sector Unprotect Operation . . . . . . . . . . . . . . . . . 17
Figure 2. In-System Sector Protect/Sector Unprotect Algorithms. . . . . 18
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Key to Switching Waveforms . . . . . . . . . . . . . . . . 37
Figure 12. Input Waveforms and Measurement Levels . . . . . . . . . . . . . . 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8. Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 14. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. Word/Byte Configuration (BYTE#) . . . . . . . . . . . . . . . . . . . . 40
Figure 15. BYTE# Timings for Read Operations . . . . . . . . . . . . . . . . . . . 41
Figure 16. BYTE# Timings for Write Operations . . . . . . . . . . . . . . . . . . 41
Erase / Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17. Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18. Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . 44
Figure 19. Data# Polling Timings (During Embedded Algorithms) . . . . 45
Figure 20. Toggle Bit Timings (During Embedded Algorithms) . . . . . . 45
Figure 21. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 11. Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 22. Temporary Sector Unprotect Timing Diagram . . . . . . . . . . 46
Figure 23. Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . 47
Table 12. Alternate CE# Controlled Erase/Program Operations . . . . . 48
Figure 24. Alternate CE# Controlled Write Operation Timings. . . . . 49
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 19
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Word/Byte Program Command Sequence . . . . . . . . . . . . . . . . . . . . . 20
Figure 3. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. S29AL008D Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Erase and Programming Performance. . . . . . . . . 49
Table 13. Latchup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 14. TSOP, SO, and BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . 50
Write Operation Status . . . . . . . . . . . . . . . . . . . . 27
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
28
28
29
29
30
30
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 51
TS 048—48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
VBK 048 - 48 Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 x 6.15 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
SO 044—44-Pin Small Outline Package . . . . . . . . . . . . . . . . . . . . . . .53
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 54
June 16, 2005 S29AL008D_00A3
S29AL008D
5
DSP and ARM Processors
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