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MT5LSDT1672AY-133B1

Description
Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, MO-161, DIMM-168
Categorystorage    storage   
File Size359KB,22 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
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MT5LSDT1672AY-133B1 Overview

Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, MO-161, DIMM-168

MT5LSDT1672AY-133B1 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
Parts packaging codeDIMM
package instructionDIMM,
Contacts168
Reach Compliance Codecompli
ECCN codeEAR99
access modeSINGLE BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N168
JESD-609 codee4
memory density1207959552 bi
Memory IC TypeSYNCHRONOUS DRAM MODULE
memory width72
Number of functions1
Number of ports1
Number of terminals168
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature65 °C
Minimum operating temperature
organize16MX72
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceGold (Au)
Terminal formNO LEAD
Terminal locationDUAL
Maximum time at peak reflow temperature30
Base Number Matches1
32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
SYNCHRONOUS
DRAM MODULE
Features
168-pin, dual in-line memory module (DIMM)
PC100- and PC133-compliant
Unbuffered
32MB (4 Meg x 72), 64MB (8 Meg x 72), 128MB (16
Meg x 72)
Supports ECC error detection and correction
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal SDRAM banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, including CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
Self Refresh Mode: 64ms, 4,096-cycle refresh for
32MB and 64MB; 64ms, 8,192-cycle refresh for
128MB
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
Gold edge contacts
MT5LSDT472A – 32MB
MT5LSDT872A(I) – 64MB
MT5LSDT1672A(I) – 128MB
For the latest data sheet, please refer to the Micron
®
Web
site:
www.micron.com/products/modules
Figure 1: 168-Pin DIMM (MO-161)
Standard 1.00in. (25.40mm)
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Operating Temperature Range
Commercial (0°C to +65°C)
Industrial (-40°C to +85°C)
• Frequency / CAS Latency
7.5ns (133 MHz) / CL = 2
7.5ns (133 MHz) / CL = 3
8ns (100 MHz) / CL = 2
NOTE:
Marking
G
Y
1
None
I
2
-13E
-133
-10E
Table 1:
Timing Parameters
SETUP
TIME
1.5
1.5
2ns
HOLD
TIME
0.8
0.8
1ns
CL = CAS (READ) latency
ACCESS TIME
MODULE
CLOCK
MARKING FREQUENCY CL = 2 CL = 3
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
9ns
5.4ns
7.5ns
1. Consult Micron for product availability.
2. Industrial Temperature option available in -133
speed only.
Table 2:
Address Table
32MB
64MB
4K
4 (BA0, BA1)
128Mb (8 Meg x 16)
4K (A0-A11)
512 (A0-A8)
1 (S0#, S2#)
128MB
8K
4 (BA0, BA1)
256Mb (16 Meg x 16)
8K (A0-A12)
512 (A0-A8)
1 (S0#, S2#)
4K
4 (BA0, BA1)
64Mb (4 Meg x 16)
4K (A0-A11)
256 (A0-A7)
1 (S0#, S2#)
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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