Preliminary
Datasheet
R1EX25032ASA00G/R1EX25064ASA00G
R1EX25032ATA00G/R1EX25064ATA00G
Serial Peripheral Interface
32k EEPROM (4-kword
8-bit)
64k EEPROM (8-kword
8-bit)
R10DS0030EJ0100
Rev.1.00
Mar. 08, 2013
105°C SPI-bus EEPROM
Description
R1EX25xxx series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and
Programmable ROM). R1EX25xxxG series improves the write/erase endurance in addition to suitable for the high
temperature industrial application that makes the best use of the feature of advanced MONOS memory cell structure.
Features
Single supply: 1.8 V to 5.5 V
Serial Peripheral Interface compatible (SPI bus)
SPI mode 0 (0,0), 3 (1,1)
Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
Power dissipation:
Standby: 2A (max)
Active (Read): 3 mA (max)
Active (Write): 3.5 mA (max)
Automatic page write: 32-byte/page
Write cycle time: 5 ms
Endurance: 1,000k Cycles @85C / 200k Cycles @ 105C
Data retention: 20 Years
Small size packages: SOP-8pin, TSSOP-8pin
Shipping tape and reel
TSSOP-8pin : 3,000 IC/reel
SOP-8pin : 2,500 IC/reel
Temperature range:
40
to
105C
Lead free product.
Halogen free products.
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics’ Sales Dept. regarding specifications.
R10DS0030EJ0100 Rev.1.00
Mar. 08, 2013
Page 1 of 20
R1EX25032ASA00G/R1EX25064ASA00G/R1EX25032ATA00G/R1EX25064ATA00G
Ordering Information
Orderable Part Numbers
R1EX25032ASA00G#U0
R1EX25064ASA00G#U0
R1EX25032ATA00G#U0
R1EX25064ATA00G#U0
Internal organization
32k bit (4096
8-bit)
64k bit (8192
8-bit)
32k bit (4096
8-bit)
64k bit (8192 8-bit)
Package
150 mil 8-pin plastic SOP
PRSP0008DF-B (FP-8DBV)
Lead free, Halogen free
8-pin plastic TSSOP
PTSP0008JC-B (TTP-8DAV)
Lead free, Halogen free
Shipping tape and reel
2,500 IC/reel
3,000 IC/reel
Pin Arrangement
8-pin SOP/TSSOP
S
Q
W
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
C
D
(Top view)
Pin Description
Pin name
C
D
Q
S
W
HOLD
V
CC
V
SS
Function
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Hold
Supply voltage
Ground
Block Diagram
Voltage detector
V
CC
High voltage generator
Control logic
S
W
C
HOLD
D
Q
Address generator
X
decoder
V
SS
Memory array
Y
decoder
Y-select & Sense amp.
Serial-parallel converter
R10DS0030EJ0100 Rev.1.00
Mar. 08, 2013
Page 2 of 20
R1EX25032ASA00G/R1EX25064ASA00G/R1EX25032ATA00G/R1EX25064ATA00G
Absolute Maximum Ratings
Parameter
Supply voltage relative to V
SS
Input voltage relative to V
SS
Operating temperature range*
1
Storage temperature range
Symbol
V
CC
Vin
Topr
Tstg
Value
0.6
to + 7.0
0.5*
2
to +7.0
40
to +105
55
to +125
Unit
V
V
C
C
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min):
3.0
V for pulse width
50 ns.
DC Operating Conditions
Parameter
Supply voltage
Input voltage
Operating temperature range
Symbol
V
CC
V
SS
V
IH
V
IL
Topr
Min
1.8
0
V
CC
0.7
0.3*
1
40
Typ
0
Max
5.5
0
V
CC
0.5*
2
V
CC
0.3
105
Unit
V
V
V
V
C
Notes: 1. V
IL
(min):
1.0
V for pulse width
50 ns.
2. V
IH
(max): V
CC
+ 1.0 V for pulse width
50 ns.
Capacitance
(Ta = +25C, f = 1 MHz)
Test conditions
Parameter
Input capacitance (D,C,
S, W ,HOLD)
Output capacitance (Q)
Note:
1.Not 100 tested.
Symbol
Cin*
1
C
I/O
*
1
Min
Typ
Max
6.0
8.0
Unit
pF
pF
Vin = 0 V
Vout = 0 V
Memory cell characteristics
(V
CC
= 1.8 V to 5.5 V)
Ta=85C
Endurance
Data retention
Note:
1. Not 100 tested.
1,000k Cycles min.
20 Years min.
Ta=105C
200k Cycles min.
20 Years min.
Notes
1
1
R10DS0030EJ0100 Rev.1.00
Mar. 08, 2013
Page 3 of 20
R1EX25032ASA00G/R1EX25064ASA00G/R1EX25032ATA00G/R1EX25064ATA00G
AC Characteristics
Test Conditions
Input pules levels:
V
IL
= V
CC
0.2
V
IH
= V
CC
0.8
Input rise and fall time:
10 ns
Input and output timing reference levels: V
CC
0.3, V
CC
0.7
Output reference levels: V
CC
0.5
Output load: 100 pF
(Ta =
40
to
105C,
V
CC
= 2.5 V to 5.5 V)
Parameter
Clock frequency
S
active setup time
S
not active setup time
S
deselect time
S
active hold time
S
not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after
HOLD
not active
Clock low hold time after
HOLD
active
Clock high setup time before
HOLD
active
Clock high setup time before
HOLD
not
active
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD
high to output low-Z
HOLD
low to output high-Z
Write time
Notes: 1. t
CH
t
CL
1/f
C
2. Not 100 tested.
Symbol
f
C
t
SLCH
t
SHCH
t
SHSL
t
CHSH
t
CHSL
t
CH
t
CL
t
CLCH
t
CHCL
t
DVCH
t
CHDX
t
HHCH
t
HLCH
t
CHHL
t
CHHH
t
SHQZ
t
CLQV
t
CLQX
t
QLQH
t
QHQL
t
HHQX
t
HLQZ
t
W
Alt
f
SCK
t
CSS1
t
CSS2
t
CS
t
CSH
t
CLH
t
CLL
t
RC
t
FC
t
DSU
t
DH
t
DIS
t
V
t
HO
t
RO
t
FO
t
LZ
t
HZ
t
WC
Min
90
90
90
90
90
90
90
20
30
70
40
60
60
0
Max
5
1
1
100
70
50
50
50
100
5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Notes
1
1
2
2
2
2
2
2
2
R10DS0030EJ0100 Rev.1.00
Mar. 08, 2013
Page 5 of 20
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