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Q33310F70021914

Description
CMOS Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size263KB,5 Pages
ManufacturerSeiko Epson Corporation
Download Datasheet Parametric View All

Q33310F70021914 Overview

CMOS Output Clock Oscillator,

Q33310F70021914 Parametric

Parameter NameAttribute value
Objectid7318451867
Reach Compliance Codeunknown
Other featuresSTANDBY; ENABLE/DISABLE FUNCTION; TR, 7 INCH
maximum descent time4 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
Installation featuresSURFACE MOUNT
Nominal operating frequency16.9344 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
Oscillator typeCMOS
Output load15 pF
physical size3.2mm x 2.5mm x 1.05mm
longest rise time4 ns
Maximum supply voltage3.6 V
Minimum supply voltage2.7 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Clock OSC
SG-310SCF
SG-310SCF 16.934400 MHz B
Product name
Product Number / Ordering code
Q33310F700219xx
Please refer to the 8.Packing information about xx (last 2 digits)
Output waveform CMOS
Pb free / Complies with EU RoHS directive
Reference weight Typ. 26 mg
1.Absolute maximum ratings
Parameter
Symbol
Maximum supply voltage
Storage temperature
Input voltage
Min.
-0.3
-40
-0.3
Typ.
-
-
-
Max.
4.2
125
Vcc+0.3
Unit
V
ºC
V
Conditions / Remarks
-
Storage as single product
ST terminal
Vcc-GND
T_stg
Vin
2.Specifications(characteristics)
Parameter
Symbol
Output frequency
Supply voltage
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Symmetry
Output voltage
Output load condition
Input voltage
Rise time
Fall time
Start-up time
Jitter
Min.
2.7
-20
-50
-
-
45
0.9Vcc
-
-
0.8Vcc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
-
Typ.
16.9344
3.3
-
-
-
-
-
-
-
-
-
-
-
-
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-
-
Max.
3.6
70
50
2.5
2.0
55
-
0.1Vcc
15
-
0.2Vcc
4
4
10
-
-
-
-
-
-
-
-
-
-
-
-
-
5
-
Unit
MHz
V
ºC
x10
-6
mA
µA
%
Conditions / Remarks
-
-
T_use
No load condition
ST = GND
50% Vcc Level L_CMOS=<15pF
IOH=-3mA
IOL=3mA
f0
Vcc
T_use
f_tol
Icc
I_std
SYM
V
OH
V
OL
L_CMOS
V
IH
V
IL
t
r
tf
t_str
t
DJ
T
RJ
t
RMS
t
p-p
t
acc
pF
CMOS Load
ST terminal
ST terminal
ns
ns
ms
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
x10
-6
0.2Vcc to 0.8Vcc Level, L_CMOS=15pF
0.2Vcc to 0.8Vcc Level, L_CMOS=15pF
t = 0 at 0.9Vcc
Deterministic Jitter
Random Jitter
δ(RMS of total distribution)
Peak to Peak
Accumulated Jitter(δ) n=2 to 50000
cycles
Off set Frequency: 12kHz to 20MHz
Off set 1Hz
Off set 10Hz
Off set 100Hz
Off set 1kHz
Off set 10kHz
Off set 100kHz
Off set 1MHz
@+25ºC first year
-
Phase jitter
Phase noise
t
PJ
L(f)
Frequency aging
f_age
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