STK1743
nvTime
™
8K x 8
AutoStore
™ nvSRAM
with Real-Time Clock
ADVANCE
FEATURES
• Data Integrity of Simtek nvSRAM Combined
with Full-Featured Real-Time Clock
• Stand-Alone Nonvolatile Memory and Time-
Keeping Solution—No Other Parts Required
• No Batteries to Fail
• Fast 25ns, 35ns and 45ns Access Times
• Software- and
AutoStore
™-Controlled
Nonvolatile Cycles
• Year 2000 Compliant with Leap Year
Compensation
• 24-Hour BCD Format
• 100-Year Data Retention over Full Industrial
Temperature Range
• Full 30-Day RTC Operation on Each Power
Loss
• Single 5V
±
10% Power Supply
DESCRIPTION
The Simtek STK1743
DIP
module houses 64Kb of
nonvolatile static
RAM
, a real-time clock (
RTC
) with
crystal and a high-value capacitor to support sys-
tems that require high reliability and ease of manu-
facturing.
READ
and
WRITE
access to all
RTC
functions and the memory is the same as a conven-
tional x 8
SRAM
. The highest eight addresses of the
RAM
support clock registers for centuries, years,
months, dates, days, hours, minutes and seconds.
Independent data resides in the integral
EEPROM
at
all times. Automatic
RECALL
on power up transfers
the
EEPROM
data to the
SRAM
, while an automatic
STORE
on power down transfers
SRAM
data to the
EEPROM
. A software
RECALL
and
STORE
are also
possible on user command.
nvTime
™ allows unlim-
ited accesses to
SRAM
, unlimited
RECALL
s and 10
6
STORE
s.
BLOCK DIAGRAM
EEPROM ARRAY
128 x 512
ROW DECODER
V
CC
STORE/
RECALL
CONTROL
PIN CONFIGURATIONS
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
5
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
128 x 512
RECALL
POWER
CONTROL
SOFTWARE
DETECT
A
0
- A
12
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
600 mil
Dual
In-Line
Module
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
RTC
PIN NAMES
A
0
- A
12
W
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
MUX
A
0
-
A
12
G
E
W
DQ
0
- DQ
7
E
G
V
CC
V
SS
March 1999
7-1
STK1743
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to V
SS
. . . . . . . . . .–0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . .–0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This a stress rating only, and functional operation of the
device at conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
I
CC
b
1
(V
CC
= 5.0V
±
10%)
INDUSTRIAL
UNITS
MIN
MAX
85
80
75
6
15
4
30
26
23
3
±1
±5
2.2
V
SS
– .5
2.4
0.4
0
70
– 40
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
85
MIN
MAX
95
85
80
7
15
4
31
27
24
3
±1
±5
V
CC
+ .5
0.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
°C
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
AVAV
= 25ns, E
≥
V
IH
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA
I
OUT
= 8mA
NOTES
PARAMETER
Average V
CC
Current
I
CC
c
2
3
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
Average V
CC
Current during
AutoStore
™ Cycle
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
I
CC
b
I
CC
c
4
I
SB
d
1
I
SB
d
2
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained at minimum cycle with outputs unloaded.
1
3
Note c: I
CC2
and I
CC4
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
Note d: E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . .1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25
°
C, f = 1.0MHz)
MAX
10
12
UNITS
pF
pF
CONDITIONS
OUTPUT
255 Ohms
∆V
= 0 to 3V
∆V
= 0 to 3V
30 pF
INCLUDING
SCOPE AND
FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
March 1999
7-2
STK1743
READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAV
f
t
AVQV
g
t
GLQV
t
AXQX
g
t
ELQX
t
EHQZ
h
t
GLQX
t
GHQZ
h
t
ELICCH
e
t
EHICCL
d
,
e
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
35
5
5
10
0
13
0
45
25
25
10
5
5
13
0
15
MIN
MAX
25
35
35
15
5
5
15
MIN
MAX
35
45
45
20
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK1743-25
(V
CC
= 5.0V
±
10%)
STK1743-35
STK1743-45
UNITS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < V
IL
and W > V
IH
; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
READ CYCLE #1:
Address Controlled
f, g
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
3
t
AVQV
DATA VALID
READ CYCLE #2:
E Controlled
f
2
t
AVAV
ADDRESS
6
E
t
ELQX
7
t
EHQZ
1
t
ELQV
1
1
t
EHICCL
G
4
8
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
ACTIVE
STANDBY
DATA VALID
t
GLQV
9
t
GHQZ
I
CC
March 1999
7-3
STK1743
WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
h, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
MIN
25
20
20
10
0
20
0
0
10
5
MAX
MIN
35
25
25
12
0
25
0
0
13
5
MAX
MIN
45
30
30
15
0
30
0
0
15
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK1743-25
(V
CC
= 5.0V
±
10%)
STK1743-35
STK1743-45
UNITS
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
WRITE CYCLE #1:
W Controlled
j
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
20
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDENCE
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
21
t
WHQX
WRITE CYCLE #2:
E Controlled
j
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDENCE
DATA IN
DATA OUT
March 1999
7-4
STK1743
AutoStore
™ / POWER-UP
RECALL
SYMBOLS
NO.
Standard
22
23
24
25
26
t
RESTORE
t
STORE
t
DELAY
V
SWITCH
V
RESET
Power-Up
RECALL
Duration
PARAMETER
MIN
MAX
550
10
1
4.0
4.5
3.9
µs
ms
µs
V
V
k
g
g
(V
CC
= 5.0V
±
10%)
STK1743
UNITS
NOTES
STORE
Cycle Duration
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
Low Voltage Reset Level
Note k:
t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
AutoStore
™ / POWER-UP
RECALL
V
CC
5V
25
V
SWITCH
26
V
RESET
AutoStore
™
23
t
STORE
POWER-UP
RECALL
22
t
RESTORE
W
DQ (DATA OUT)
24
t
DELAY
POWER-UP
RECALL
BROWN OUT
NO
STORE
DUE TO
NO SRAM WRITES
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore
™
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore
™
RECALL
WHEN
V
CC
RETURNS
ABOVE V
SWITCH
March 1999
7-5
京公网安备 11010802033920号
EEWORLD
