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LY62W1024LL-70SLIT

Description
SRAM,
Categorystorage    storage   
File Size771KB,20 Pages
ManufacturerLyontek
Websitehttp://www.lyontek.com.tw/index.html
Download Datasheet Parametric View All

LY62W1024LL-70SLIT Overview

SRAM,

LY62W1024LL-70SLIT Parametric

Parameter NameAttribute value
Objectid8322626038
package instructionTSOP1,
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time70 ns
JESD-30 codeR-PDSO-G32
JESD-609 codee3
length18.4 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP1
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Maximum seat height1.2 mm
Maximum slew rate0.05 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width8 mm
LY62W1024
Rev. 1.11
128K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Description
Initial Issue
Revised I
SB1
LL/LLI-LLE(max)= 50/100
A
=> 20/50
A
I
DR
LL/LLI-LLE(max)= 20/40
A
=> 12/30
A
Added SL Spec.
Revised typos in
FEATURES
Revised I
SB1
/I
DR(MAX.)
Added I
SB1
/I
DR
values when T
A
= 25
and T
A
= 40
Revised
FEATURES
&
ORDERING INFORMATION
Lead free and green package available
to
Green package available
Added packing type in
ORDERING INFORMATION
Revised V
TERM
to V
T1
and V
T2
Deleted T
SOLDER
in
ABSOLUTE MAXIMUN RATINGS
Revised
PACKAGE OUTLINE DIMENSION
in page 10/11/12/13
Revised
ORDERING INFORMATION
in page 14
Deleted E Grade
Revised
PIN CONFIGURATION
in page 2
Correct
ORDERING INFORMATION
Typo.
Added top view of BGA in
PIN CONFIGURATION
Deleted E Grade in
ORDERING INFORMATION
Deleted
WRITE CYCLE
Notes :
1. WE#, CE# must be high or CE2 must be low during all address transitions
in page 7
Revised
GENERAL DESCRIPTION
in page 1
Revised
32-pin TSOP I & 36-ball TFBGA Package Outline Dimension
Issue Date
Aug.28.2005
Mar.30.2006
Nov.2.2007
May.6.2008
Mar.30.2009
Rev. 1.5
Rev. 1.6
Rev. 1.7
Rev. 1.8
Rev. 1.9
May.7.2010
Aug.30.2010
Aug.9.2011
Apr.06.2012
May.20.2016
Rev. 1.10
Rev. 1.11
Jun.28.2016
Feb.06.2017
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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