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LY62W1024PL-70LL

Description
Standard SRAM, 128KX8, 70ns, CMOS, PDIP32,
Categorystorage    storage   
File Size771KB,20 Pages
ManufacturerLyontek
Websitehttp://www.lyontek.com.tw/index.html
Environmental Compliance
Download Datasheet Parametric View All

LY62W1024PL-70LL Overview

Standard SRAM, 128KX8, 70ns, CMOS, PDIP32,

LY62W1024PL-70LL Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid8322626051
package instructionDIP, DIP32,.6
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-PDIP-T32
length41.91 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.6
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
power supply3/5 V
Certification statusNot Qualified
Maximum seat height4.064 mm
Maximum standby current0.000012 A
Minimum standby current1.5 V
Maximum slew rate0.05 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width15.24 mm
LY62W1024
Rev. 1.11
128K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Description
Initial Issue
Revised I
SB1
LL/LLI-LLE(max)= 50/100
A
=> 20/50
A
I
DR
LL/LLI-LLE(max)= 20/40
A
=> 12/30
A
Added SL Spec.
Revised typos in
FEATURES
Revised I
SB1
/I
DR(MAX.)
Added I
SB1
/I
DR
values when T
A
= 25
and T
A
= 40
Revised
FEATURES
&
ORDERING INFORMATION
Lead free and green package available
to
Green package available
Added packing type in
ORDERING INFORMATION
Revised V
TERM
to V
T1
and V
T2
Deleted T
SOLDER
in
ABSOLUTE MAXIMUN RATINGS
Revised
PACKAGE OUTLINE DIMENSION
in page 10/11/12/13
Revised
ORDERING INFORMATION
in page 14
Deleted E Grade
Revised
PIN CONFIGURATION
in page 2
Correct
ORDERING INFORMATION
Typo.
Added top view of BGA in
PIN CONFIGURATION
Deleted E Grade in
ORDERING INFORMATION
Deleted
WRITE CYCLE
Notes :
1. WE#, CE# must be high or CE2 must be low during all address transitions
in page 7
Revised
GENERAL DESCRIPTION
in page 1
Revised
32-pin TSOP I & 36-ball TFBGA Package Outline Dimension
Issue Date
Aug.28.2005
Mar.30.2006
Nov.2.2007
May.6.2008
Mar.30.2009
Rev. 1.5
Rev. 1.6
Rev. 1.7
Rev. 1.8
Rev. 1.9
May.7.2010
Aug.30.2010
Aug.9.2011
Apr.06.2012
May.20.2016
Rev. 1.10
Rev. 1.11
Jun.28.2016
Feb.06.2017
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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