W39L010Q-70B datasheet, PDF - EEWORLD Datasheet

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W39L010Q-70B: Description128K X 8 CMOS FLASH MEMORY; Categorystorage storage; File Size319KB，27 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W39L010Q-70B Overview

128K X 8 CMOS FLASH MEMORY

W39L010Q-70B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	TSOP
package instruction	8 X 14 MM, STSOP-32
Contacts	32
Reach Compliance Code	_compli
ECCN code	EAR99
Maximum access time	70 ns
command user interface	YES
Data polling	YES
JESD-30 code	R-PDSO-G32
JESD-609 code	e0
length	12.4 mm
memory density	1048576 bi
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	32
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP32,.56,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Programming voltage	3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Department size	4K
Maximum standby current	0.00005 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
switch bit	YES
type	NOR TYPE
width	8 mm
Base Number Matches	1

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W39L010

128K

8 CMOS FLASH MEMORY

Table of Contents-

GENERAL DESCRIPTION ......................................................................................................... 3

FEATURES ................................................................................................................................. 3

PIN CONFIGURATIONS ............................................................................................................ 4

BLOCK DIAGRAM ...................................................................................................................... 4

PIN DESCRIPTION..................................................................................................................... 4

FUNCTIONAL DESCRIPTION ................................................................................................... 5

6.1

Device Bus Operation..................................................................................................... 5

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

Read Mode.......................................................................................................................5

Write Mode .......................................................................................................................5

Standby Mode ..................................................................................................................5

Output Disable Mode........................................................................................................5

Auto-select Mode..............................................................................................................5

Boot Block Operation........................................................................................................6

Write Pulse "Glitch" Protection .........................................................................................6

Logical Inhibit ...................................................................................................................6

Power-up Write Inhibit ......................................................................................................6

Read Command ...............................................................................................................7

Auto-select Command ......................................................................................................7

Byte Program Command ..................................................................................................7

Chip Erase Command ......................................................................................................8

Page Erase Command .....................................................................................................8

DQ7: Data Polling.............................................................................................................9

DQ6: Toggle Bit................................................................................................................9

6.2

Data Protection ............................................................................................................... 6

6.2.1

6.2.2

6.2.3

6.2.4

6.3

Command Definitions ..................................................................................................... 7

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.4

Write Operation Status ................................................................................................... 9

6.4.1

6.4.2

TABLE OF OPERATING MODES ............................................................................................ 10

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Device Bus Operations ................................................................................................. 10

Auto-select Codes (High Voltage Method) ................................................................... 10

Command Definitions ................................................................................................... 11

Embedded Programming Algorithm ............................................................................. 12

Embedded Erase Algorithm.......................................................................................... 13

Embedded #Data Polling Algorithm.............................................................................. 14

Embedded Toggle Bit Algorithm ................................................................................... 14

Publication Release Date: January 9, 2004

Revision A4

-1-

W39L010

7.8

7.9

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

9.1

9.2

9.3

9.4

9.5

9.6

9.7

10.

11.

12.

Boot Block Lockout Enable Flow Chart ........................................................................ 15

Software Product Identification and Boot Block Lockout Detection Flow Chart........... 16

Absolute maximum Ratings .......................................................................................... 17

DC Operating Characteristics....................................................................................... 17

Pin Capacitance............................................................................................................ 17

AC Test Conditions....................................................................................................... 18

AC Test Load and Waveform ....................................................................................... 18

Read Cycle Timing Parameters.................................................................................... 19

Write Cycle Timing Parameters.................................................................................... 19

Power-up Timing........................................................................................................... 20

Data Polling and Toggle Bit Timing Parameters .......................................................... 20

Read Cycle Timing Diagram......................................................................................... 21

#WE Controlled Command Write Cycle Timing Diagram............................................. 21

#CE Controlled Command Write Cycle Timing Diagram.............................................. 22

Chip Erase Timing Diagram ......................................................................................... 22

Page Erase Timing Diagram ........................................................................................ 23

#DATA Polling Timing Diagram .................................................................................... 23

Toggle Bit Timing Diagram ........................................................................................... 24

ELECRICAL CHARACTERISTICS ........................................................................................... 17

TIMING WAVEFORMS ............................................................................................................. 21

ORDERING INFORMATION .................................................................................................... 25

HOW TO READ THE TOP MARKING...................................................................................... 25

PACKAGE DIMENSIONS ......................................................................................................... 26

12.1

12.2

32-pin PLCC ................................................................................................................. 26

32-pin STSOP (8 x 14 mm) .......................................................................................... 26

13.

VERSION HISTORY ................................................................................................................. 27

-2-

W39L010

6. FUNCTIONAL DESCRIPTION

6.1 Device Bus Operation

6.1.1

Read Mode

The read operation of the W39L010 is controlled by #CE and #OE, both of which have to be low for

the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip

is de-selected and only standby power will be consumed. #OE is the output control and is used to

gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is

high. Refer to the timing waveforms for further details.

6.1.2

Write Mode

Device erasure and programming are accomplished via the command register. The contents of the

of the device.

The command register itself does not occupy any addressable memory location. The register is a

latch used to store the commands, along with the address and data information needed to execute the

command. The command register is written to bring #WE to logic low state, while #CE is at logic low

state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,

whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens

first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing

parameters.

6.1.3

Standby Mode

There are two ways to implement the standby mode on the W39L010 device, both using the #CE pin.

A CMOS standby mode is achieved with the

#CE input held at V

±0.3V.

Under this condition the current

is typically reduced to less than 20

µA.

A TTL standby mode is achieved with the #CE pin held at V

Under this condition the current is typically reduced to 2 mA.

In the standby mode the outputs are in the high impedance state, independent of the #OE input.

6.1.4

Output Disable Mode

With the #OE input at a logic high level (V

), output from the device is disabled. This will cause the

output pins to be in a high impedance state.

6.1.5

Auto-select Mode

The auto-select mode allows the reading of a binary code from the device and will identify its

manufacturer and type. This mode is intended for use by programming equipment for the purpose of

automatically matching the device to be programmed with its corresponding programming algorithm.

This mode is functional over the entire temperature range of the device.

To activate this mode, the programming equipment must force V

(11.5V to 12.5V) on address pin

A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from

to V

. All addresses are don′t cares except A0 and A1 (see "Auto-select Codes").

-5-

Publication Release Date: January 9, 2004

Revision A4

W39L010Q-70B Related Products

	W39L010Q-70B	W39L010	W39L010P-70	W39L010P-70B	W39L010P-90	W39L010Q-70	W39L010Q-90
Description	128K X 8 CMOS FLASH MEMORY	128K X 8 CMOS FLASH MEMORY	128K X 8 CMOS FLASH MEMORY	128K X 8 CMOS FLASH MEMORY	128K X 8 CMOS FLASH MEMORY	128K X 8 CMOS FLASH MEMORY	128K X 8 CMOS FLASH MEMORY
Is it Rohs certified?	incompatible	-	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	TSOP	-	QFJ	QFJ	QFJ	TSOP	TSOP
package instruction	8 X 14 MM, STSOP-32	-	QCCJ, LDCC32,.5X.6	PLASTIC, LCC-32	QCCJ, LDCC32,.5X.6	TSSOP, TSSOP32,.56,20	TSSOP, TSSOP32,.56,20
Contacts	32	-	32	32	32	32	32
Reach Compliance Code	_compli	-	unknow	_compli	unknow	unknow	unknow
ECCN code	EAR99	-	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	70 ns	-	70 ns	70 ns	90 ns	70 ns	90 ns
command user interface	YES	-	YES	YES	YES	YES	YES
Data polling	YES	-	YES	YES	YES	YES	YES
JESD-30 code	R-PDSO-G32	-	R-PQCC-J32	R-PQCC-J32	R-PQCC-J32	R-PDSO-G32	R-PDSO-G32
JESD-609 code	e0	-	e0	e0	e0	e0	e0
length	12.4 mm	-	13.97 mm	13.97 mm	13.97 mm	12.4 mm	12.4 mm
memory density	1048576 bi	-	1048576 bi	1048576 bi	1048576 bi	1048576 bi	1048576 bi
Memory IC Type	FLASH	-	FLASH	FLASH	FLASH	FLASH	FLASH
memory width	8	-	8	8	8	8	8
Number of functions	1	-	1	1	1	1	1
Number of departments/size	32	-	32	32	32	32	32
Number of terminals	32	-	32	32	32	32	32
word count	131072 words	-	131072 words	131072 words	131072 words	131072 words	131072 words
character code	128000	-	128000	128000	128000	128000	128000
Operating mode	ASYNCHRONOUS	-	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	-	70 °C	70 °C	70 °C	70 °C	70 °C
organize	128KX8	-	128KX8	128KX8	128KX8	128KX8	128KX8
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	-	QCCJ	QCCJ	QCCJ	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP32,.56,20	-	LDCC32,.5X.6	LDCC32,.5X.6	LDCC32,.5X.6	TSSOP32,.56,20	TSSOP32,.56,20
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	PARALLEL	-	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	240	-	NOT SPECIFIED	225	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Programming voltage	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	-	3.56 mm	3.56 mm	3.56 mm	1.2 mm	1.2 mm
Department size	4K	-	4K	4K	4K	4K	4K
Maximum standby current	0.00005 A	-	0.00005 A	0.00005 A	0.00005 A	0.00005 A	0.00005 A
Maximum slew rate	0.03 mA	-	0.03 mA	0.03 mA	0.03 mA	0.03 mA	0.03 mA
Maximum supply voltage (Vsup)	3.6 V	-	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	-	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	-	YES	YES	YES	YES	YES
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	TIN LEAD	Tin/Lead (Sn/Pb)	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	GULL WING	-	J BEND	J BEND	J BEND	GULL WING	GULL WING
Terminal pitch	0.5 mm	-	1.27 mm	1.27 mm	1.27 mm	0.5 mm	0.5 mm
Terminal location	DUAL	-	QUAD	QUAD	QUAD	DUAL	DUAL
Maximum time at peak reflow temperature	30	-	NOT SPECIFIED	30	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
switch bit	YES	-	YES	YES	YES	YES	YES
type	NOR TYPE	-	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
width	8 mm	-	11.43 mm	11.43 mm	11.43 mm	8 mm	8 mm
Base Number Matches	1	-	1	1	1	1	1

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