The S-24C0XA is a series of 2-wired, low power 1K/2K/4K
with a wide operating range. They are organized as 12
256-word
×
8-bit, and 512-word
×
8-bit, respectively. Eac
page write, and sequential read.
The time for byte write and page write is the same, i. e.,
during operation at 5 V
±
10%.
Features
•
Low power consumption
Standby: 1.0
µ
A Max.
•
Endurance:
10
6
cycles/word
10 years
Operating: 0.4 mA Max.
0.3 mA Max.
•
Wide operating voltage range
(V
CC
=5.5 V)
(V
CC
=5.5 V)
(V
CC
=3.3 V)
•
Data retention:
•
Write protection:
•
S-24C01A:
•
S-24C02A:
•
S-24C04A:
S-24C02A, S-24C
1 kbits
2 kbits
4 kbits
Write:
Read:
•
Page write
2.5 to 5.5 V
1.8 to 5.5 V
8 bytes (S-24C01A, S-24C02A)
16 bytes (S-24C04A)
Package
8-pin DIP
8-pin SOP
(PKG drawing code : DP008-A,DP008-C)
(PKG drawing code : FJ008-D,FJ008-E)
Pin Assignment
8-pin DIP
Top view
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
TEST/WP
SCL
SDA
A0
A1
A2
GND
8-pin SOP
Top view
1
2
3
4
8
7
6
5
VCC
TEST/WP
SCL
SDA
S-24C01ADPx-uu
S-24C02ADPx-uu
S-24C04ADPx-uu
S-24C01AFJA-zz-uuw
S-24C02AFJA-zz-uuw
S-24C04AFJA-zz-uuw
* Lower-case letters x, uu, zz and
depending on the packing form.
See Ordering Information and
Figure 1
Pin Functions
Table 1
Name
A0
A1
A2
GND
SDA
SCL
TEST/WP
VCC
Pin Number
DIP
SOP
1
1
2
2
3
3
4
4
5
5
6
6
7
8
7
8
Function
Address input (no connection in the S-24C04A*)
Address input
Address input
Ground
Serial data input/output
Serial clock input
TEST pin (S-24C01A): Connected to GND.
WP (Write Protection) pin (S-24C02A, S-24C04A):
* Connected to Vcc:
Protection valid
* Connected to GND: Protection invalid
Power supply
* When in us
GND or Vc
Seiko Instruments Inc.
Power supply voltage
V
CC
Write Operation
V
CC
=2.5 to 5.5V
V
CC
=1.8 to 2.5V
V
CC
=2.5 to 5.5V
V
CC
=1.8 to 2.5V
—
2.5
0.7×V
CC
0.8×V
CC
0.0
0.0
-40
—
—
—
—
—
—
5.5
V
CC
V
CC
0.3×V
CC
0.2×V
CC
+85
High level input voltage
V
IH
Low level input voltage
Operating temperature
V
IL
T
opr
Pin Capacitance
Table 4
(Ta=25°C, f=1.0
Parameter
Input capacitance
Input/output capacitance
Symbol
C
IN
C
I / O
Conditions
V
IN
=0 V (SCL, A0, A1, A2, WP)
V
I / O
=0 V (SDA)
Min.
—
—
Typ.
—
—
Ma
1
1
Endurance
Table 5
Parameter
Endurance
Symbol
N
W
Min.
10
6
Typ.
—
Max.
—
Unit
cycles/word
Seiko Instruments Inc.
R=1.0k
Input pulse voltage
Input pulse rising/falling time
Output judgment voltage
Output load
0.1×V
CC
to 0.9×V
CC
20 ns
0.5×V
CC
100 pF+ Pullup resistance 1.0 kΩ
SDA
C=
Figure 3
Output Load
Table 9
Parameter
SCL clock frequency
SCL clock time "L"
SCL clock time"H"
SDA output delay time
SDA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL
·
SDA rising time
SCL
·
SDA falling time
Bus release time
Noise suppression time
Symbol
f
SCL
t
LOW
t
HIGH
t
AA
t
DH
t
SU.STA
t
HD.STA
t
SU.DAT
t
HD.DAT
t
SU.STO
t
R
t
F
t
BUF
t
I
V
CC
=1.8V to 5.5V
Min.
0
4.7
4.0
0.3
0.3
4.7
4.0
50
0
4.7
Typ.
Max.
100
—
—
4.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.5
—
—
—
—
—
—
1.0
0.3
—
100
t
F
SCL
t
HIGH
t
LOW
t
R
t
SU.STA
t
HD.STA
t
HD.DAT
t
SU.DAT
t
SDA IN
t
AA
SDA OUT
invalid
valid
t
DH
Figure 4
Bus Timing
Seiko Instruments Inc.
FPGA/CPLD
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