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LC4128ZC-75M132C

Description
cpld - complex programmable logic devices 1.8V 96 I/O
Categorysemiconductor    Other integrated circuit (IC)   
File Size330KB,95 Pages
ManufacturerAll Sensors
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LC4128ZC-75M132C Overview

cpld - complex programmable logic devices 1.8V 96 I/O

LC4128ZC-75M132C Parametric

Parameter NameAttribute value
ManufactureLattice
Product CategoryCPLD - Complex Programmable Logic Devices
RoHSN
ProducispMACH 4128
Number of Macrocells128
Number of Logic Array Blocks - LABs8
Maximum Operating Frequency220 MHz
Delay Time4.2 ns
Number of I/Os96
Operating Supply Voltage1.8 V
Maximum Operating Temperature+ 90 C
Mounting StyleSMD/SMT
Package / CaseCSBGA-132
Memory TypeEEPROM
Minimum Operating Temperature0 C
Number of Product Terms per Mac80
Operating Supply Curre0.168 mA
PackagingTray
Factory Pack Quantity360
Supply Voltage - Max1.9 V
Supply Voltage - Mi1.7 V
ispMACH 4000V/B/C/Z Family
February 2006
TM
Coolest Power
C
TM
3.3V/2.5V/1.8V In-System Programmable
SuperFAST
TM
High Density PLDs
Data Sheet
Features
High Performance
Broad Device Offering
• Multiple temperature range support
– Commercial: 0 to 90°C junction (T
j
)
– Industrial: -40 to 105°C junction (T
j
)
– Automotive: -40 to 130°C junction (T
j
)
• f
MAX
= 400MHz maximum operating frequency
• t
PD
= 2.5ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
Easy System Integration
• Superior solution for power sensitive consumer
applications
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Operation with 3.3V (4000V), 2.5V (4000B) or
1.8V (4000C/Z) supplies
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V In-System Programmable
(ISP™) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free package options
Ease of Design
• Enhanced macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-Fit
TM
and refit
• Fast path, SpeedLocking
TM
Path, and wide-PT
path
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
Zero Power (ispMACH 4000Z) and Low
Power (ispMACH 4000V/B/C)
Typical static current 10µA (4032Z)
Typical static current 1.3mA (4000C)
1.8V core low dynamic power
ispMACH 4000Z operational down to 1.6V V
CC
Table 1. ispMACH 4000V/B/C Family Selection Guide
ispMACH
4032V/B/C
Macrocells
I/O + Dedicated
Inputs
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
f
MAX
(MHz)
Supply Voltages (V)
Pins/Package
32
30+2/32+4
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
ispMACH
4064V/B/C
64
30+2/32+4/
64+10
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
100 TQFP
ispMACH
4128V/B/C
128
64+10/92+4/
96+4
2.7
1.8
2.7
333
3.3/2.5/1.8V
ispMACH
4256V/B/C
256
64+10/96+14/
128+4/160+4
3.0
2.0
2.7
322
3.3/2.5/1.8V
ispMACH
4384V/B/C
384
128+4/192+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
ispMACH
4512V/B/C
512
128+4/208+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
100 TQFP
128 TQFP
144 TQFP
1
100 TQFP
144 TQFP
1
176 TQFP
256 fpBGA
2
176 TQFP
256 fpBGA
176 TQFP
256 fpBGA
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O configurations.
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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