2014.04.08
Stratix V Device Overview
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Many of the Stratix
®
V devices and features are enabled in the Quartus
®
II software version 13.0. The
remaining devices and features will be enabled in future versions of the Quartus II software.
Altera’s 28-nm Stratix V FPGAs include innovations such as an enhanced core architecture, integrated
transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual property
(IP) blocks. With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices
optimized for:
• Bandwidth-centric applications and protocols, including PCI Express
®
(PCIe
®
) Gen3
• Data-intensive applications for 40G/100G and beyond
• High-performance, high-precision digital signal processing (DSP) applications
Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of
applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-risk,
low-cost path to HardCopy
®
V ASICs.
Related Information
•
Stratix V Device Handbook: Known Issues
Lists the planned updates to the
Stratix V Device Handbook
chapters.
•
Upcoming Stratix V Device Features
Stratix V Family Variants
The Stratix V device family contains the GT, GX, GS, and E variants.
Stratix V GT
devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are optimized for applications that
require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communications
systems and optical test systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and GX
channels, respectively.
Stratix V GX
devices offer up to 66 integrated transceivers with 14.1-Gbps data rate capability. These
transceivers also support backplane and optical interface applications. These devices are optimized for high-
performance, high-bandwidth applications such as 40G/100G optical transport, packet processing, and
traffic management found in wireline, military communications, and network test equipment markets.
Stratix V GS
devices have an abundance of variable precision DSP blocks, supporting up to 3,926 18x18 or
1,963 27x27 multipliers. In addition, Stratix V GS devices offer integrated transceivers with 14.1-Gbps data
rate capability. These transceivers also support backplane and optical interface applications. These devices
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no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
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Stratix V Features Summary
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2014.04.08
are optimized for transceiver-based DSP-centric applications found in wireline, military, broadcast, and
high-performance computing markets.
Stratix V E
devices offer the highest logic density within the Stratix V family with nearly one million logic
elements (LEs) in the largest device. These devices are optimized for applications such as ASIC and system
emulation, diagnostic imaging, and instrumentation.
Common to all Stratix V family variants are a rich set of high-performance building blocks, including a
redesigned adaptive logic module (ALM), 20 Kbit (M20K) embedded memory blocks, variable precision
DSP blocks, and fractional phase-locked loops (PLLs). All of these building blocks are interconnected by
Altera’s superior multi-track routing architecture and comprehensive fabric clocking network.
Also common to Stratix V devices is the new Embedded HardCopy Block, which is a customizable hard IP
block that leverages Altera’s unique HardCopy ASIC capabilities. The Embedded HardCopy Block in Stratix V
FPGAs is used to harden IP instantiation of PCIe Gen3, Gen2, and Gen1.
Stratix V Features Summary
Table 1: Summary of Features for Stratix V Devices
Feature
Description
Technology
Low-power serial
transceivers
• 28-nm TSMC process technology
• 0.85-V or 0.9-V core voltage
• 28.05-Gbps transceivers on Stratix V GT devices
• Electronic dispersion compensation (EDC) for XFP, SFP+, QSFP, CFP optical
module support
• Adaptive linear and decision feedback equalization
• Transmitter pre-emphasis and de-emphasis
• Dynamic reconfiguration of individual channels
• On-chip instrumentation (EyeQ non-intrusive data eye monitoring)
• 600-Megabits per second (Mbps) to 12.5-Gbps data rate capability
•
•
•
•
1.6-Gbps LVDS
1,066-MHz external memory interface
On-chip termination (OCT)
1.2-V to 3.3-V interfacing for all Stratix V devices
Backplane capability
General-purpose I/Os
(GPIOs)
Embedded HardCopy
Block
• PCIe Gen3, Gen2, and Gen1 complete protocol stack, x1/x2/x4/x8 end point
and root port
Embedded transceiver hard • Interlaken physical coding sublayer (PCS)
IP
• Gigabit Ethernet (GbE) and XAUI PCS
• 10G Ethernet PCS
• Serial RapidIO
®
(SRIO) PCS
• Common Public Radio Interface (CPRI) PCS
• Gigabit Passive Optical Networking (GPON) PCS
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Stratix V Family Plan
3
Feature
Description
Power management
High-performance core
fabric
• Programmable Power Technology
• Quartus II integrated PowerPlay Power Analysis
• Enhanced ALM with four registers
• Improved routing architecture reduces congestion and improves compile
times
Embedded memory blocks • M20K: 20-Kbit with hard error correction code (ECC)
• MLAB: 640-bit
Variable precision DSP
blocks
• Up to 600 MHz performance
• Natively support signal processing with precision ranging from 9x9 up to
54x54
• New native 27x27 multiply mode
• 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
• Embedded internal coefficient memory
• Pre-adder/subtractor improves efficiency
• Increased number of outputs allows more independent multipliers
• Fractional mode with third-order delta-sigma modulation
• Integer mode
• Precision clock synthesis, clock delay compensation, and zero delay buffer
(ZDB)
• 800-MHz fabric clocking
• Global, quadrant, and peripheral clock networks
• Unused clock networks can be powered down to reduce dynamic power
•
•
•
•
•
Serial and parallel flash interface
Enhanced advanced encryption standard (AES) design security features
Tamper protection
Partial and dynamic reconfiguration
Configuration via Protocol (CvP)
Fractional PLLs
Clock networks
Device configuration
High-performance
packaging
• Multiple device densities with identical package footprints enables seamless
migration between different FPGA densities
• FBGA packaging with on-package decoupling capacitors
• Lead and RoHS-compliant lead-free options
—
HardCopy V migration
Stratix V Family Plan
The following tables list the features of the different Stratix V devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
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Stratix V Family Plan
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Table 2: Stratix V GT Device Features
Feature
5SGTC5
5SGTC7
Logic Elements (K)
Registers (K)
28.05/12.5-Gbps Transceivers
PCIe hard IP Blocks
Fractional PLLs
M20K Memory Blocks
M20K Memory (MBits)
Variable Precision Multipliers (18x18)
Variable Precision Multipliers (27x27)
DDR3 SDRAM x72 DIMM Interfaces
(1)
425
642
4/32
1
28
2,304
45
512
256
4
622
939
4/32
1
28
2,560
50
512
256
4
User I/Os , Full-Duplex LVDS, 28.05/12.5-Gbps Transceivers
Package
(2) (3)
5SGTC5
5SGTC7
KF40-F1517
(4)
Table 3: Stratix V GX Device Features
Features
600, 150, 36
600, 150, 36
5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB 5SGXB5 5SGXB6 5SGXB9
5SGXBB
Logic
Elements
(K)
Registers
(K)
340
420
490
622
840
952
490
597
840
952
513
634
740
939
1,268
1,437
740
66
1 or 4
902
66
1 or 4
1,268
66
1 or 4
1,437
66
1 or 4
14.1-Gbps 12, 24, 24 or 36 24, 36,
Transceivers or 36
or 48
PCIe hard
IP Blocks
1 or 2
1 or 2
24, 36, 36 or 48 36 or 48
or 48
1, 2, or 1, 2, or 1, 2, or 1, 2, or
4
4
4
4
(1)
(2)
(3)
(4)
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os
includes transceiver I/Os.
Packages are flipchip ball grid array (1.0-mm pitch).
Each package row offers pin migration (common board footprint) for all devices in the row.
Migration between select Stratix V GT devices and Stratix V GX devices is available. For more information,
refer to
Table 6
and to
AN 644: Migration Between Stratix V GX and Stratix V GT Devices.
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Stratix V Family Plan
5
Features
5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB 5SGXB5 5SGXB6 5SGXB9
5SGXBB
Fractional
PLLs
M20K
Memory
Blocks
M20K
Memory
(MBits)
Variable
Precision
Multipliers
(18x18)
Variable
Precision
Multipliers
(27x27)
DDR3
SDRAM
x72 DIMM
Interfaces
20
(5)
957
24
1,900
28
2,304
28
2,560
28
2,640
28
2,640
24
2,100
24
2,660
32
2,640
32
2,640
19
37
45
50
52
52
41
52
52
52
512
512
512
512
704
704
798
798
704
704
256
256
256
256
352
352
399
399
352
352
4
4
6
6
6
6
4
4
4
4
User I/Os , Full-Duplex LVDS, 14.1-Gbps Transceivers
Package
(2) (3)
(6) (7)
(1)
5SGXA3 5SGXA4 5SGXA5 5SGXA7 5SGXA9 5SGXAB 5SGXB5 5SGXB6 5SGXB9
5SGXBB
EH29-
H780
HF35-
F1152
(8)
KF35-
F1152
360, 90,
12
H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
432,
552,
552,
552,
108, 24 138, 24 138, 24 138, 24
432,
432,
432,
432,
108, 36 108, 36 108, 36 108, 36
(5)
(6)
(7)
(8)
The F1517 package contains 24 PLLs. The other packages with this device contain 20 PLLs.
LVDS counts are full duplex channels. Each full duplex channel is one transmitter (TX) pair plus one receiver
(RX) pair.
A superscript
H
after the number of transceivers indicates that this device is only available in a hybrid package.
Hybrid packages are slightly larger than conventional FBGAs. Refer to Altera’s packaging documentation for
more information.
Migration between select Stratix V GX devices and Stratix V GS devices is available. For more information,
refer to
Table 6.
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