iCE40LP1K-CM81 datasheet, PDF - EEWORLD Datasheet

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iCE40LP1K-CM81: Descriptionfpga - field programmable gate array ice40lp 1280 luts 1.2V ultra low-power; Categorysemiconductor Other integrated circuit (IC); File Size17MB，215 Pages; ManufacturerAll Sensors; Environmental Compliance

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iCE40LP1K-CM81 Overview

fpga - field programmable gate array ice40lp 1280 luts 1.2V ultra low-power

iCE40LP1K-CM81 Parametric

Parameter Name	Attribute value
Manufacture	Lattice
Product Category	FPGA - Field Programmable Gate Array
RoHS	Yes
Produc	iCE40 LP
Number of Logic Elements	1280
Number of Logic Array Blocks - LABs	160
Total Memory	64 kbi
Number of I/Os	63
Operating Supply Voltage	1.2 V
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	CBGA-81
M4K Memory	64 kbi
Maximum Operating Frequency	533 MHz
Minimum Operating Temperature	- 40 C
Number of Gates	1280
Packaging	Tray
Factory Pack Quantity	490

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iCE40™ LP/HX/LM Family Handbook

HB1011 Version 01.2, November 2013

iCE40 LP/HX/LM Family

Handbook

Table of Contents

October 2013

Section I. iCE40 LP/HX Family Data Sheet

Introduction

Features ............................................................................................................................................................. 1-1

Introduction ........................................................................................................................................................ 1-2

Architecture

Architecture Overview ........................................................................................................................................ 2-1

PLB Blocks................................................................................................................................................ 2-2

Routing...................................................................................................................................................... 2-3

Clock/Control Distribution Network ........................................................................................................... 2-3

sysCLOCK Phase Locked Loops (PLLs) .................................................................................................. 2-4

sysMEM Embedded Block RAM Memory ................................................................................................. 2-5

sysIO ......................................................................................................................................................... 2-7

sysIO Buffer .............................................................................................................................................. 2-8

Non-Volatile Configuration Memory .......................................................................................................... 2-9

Power On Reset...................................................................................................................................... 2-10

Programming and Configuration ...................................................................................................................... 2-10

Power Saving Options............................................................................................................................. 2-10

DC and Switching Characteristics

Absolute Maximum Ratings ............................................................................................................................... 3-1

Recommended Operating Conditions ................................................................................................................ 3-1

Power Supply Ramp Rates ................................................................................................................................ 3-2

Power-On-Reset Voltage Levels........................................................................................................................ 3-2

ESD Performance .............................................................................................................................................. 3-2

DC Electrical Characteristics.............................................................................................................................. 3-3

Static Supply Current – LP Devices ................................................................................................................... 3-3

Static Supply Current – HX Devices .................................................................................................................. 3-4

Programming NVCM Supply Current – LP Devices........................................................................................... 3-4

Programming NVCM Supply Current – HX Devices .......................................................................................... 3-5

Peak Startup Supply Current – LP Devices ....................................................................................................... 3-5

Peak Startup Supply Current – HX Devices....................................................................................................... 3-6

sysIO Recommended Operating Conditions...................................................................................................... 3-6

sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-6

sysIO Differential Electrical Characteristics ....................................................................................................... 3-7

LVDS25..................................................................................................................................................... 3-7

subLVDS ................................................................................................................................................... 3-7

LVDS25E Emulation .......................................................................................................................................... 3-8

SubLVDS Emulation .......................................................................................................................................... 3-9

Typical Building Block Function Performance – LP Devices............................................................................ 3-10

Pin-to-Pin Performance (LVCMOS25) .................................................................................................... 3-10

Register-to-Register Performance .......................................................................................................... 3-10

Typical Building Block Function Performance – HX Devices ........................................................................... 3-10

Pin-to-Pin Performance (LVCMOS25) .................................................................................................... 3-10

Register-to-Register Performance .......................................................................................................... 3-10

Derating Logic Timing ...................................................................................................................................... 3-11

Maximum sysIO Buffer Performance ............................................................................................................... 3-11

iCE40 Family Timing Adders............................................................................................................................ 3-11

iCE40 External Switching Characteristics – LP Devices.................................................................................. 3-13

iCE40 External Switching Characteristics – HX Devices ................................................................................. 3-15

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Table of Contents

iCE40 LP/HX/LM Family Handbook

sysCLOCK PLL Timing .................................................................................................................................... 3-16

SPI Master or NVCM Configuration Time ....................................................................................................... 3-17

sysCONFIG Port Timing Specifications ........................................................................................................... 3-18

Switching Test Conditions................................................................................................................................ 3-20

Pinout Information

Signal Descriptions ............................................................................................................................................ 4-1

Pin Information Summary................................................................................................................................... 4-3

Pin Information Summary, Continued ................................................................................................................ 4-4

Ordering Information

iCE40 Part Number Description ......................................................................................................................... 5-1

Ultra Low Power (LP) Devices .................................................................................................................. 5-1

High Performance (HX) Devices ............................................................................................................... 5-1

Ordering Information .......................................................................................................................................... 5-1

Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging......................................... 5-2

Supplemental Information

For Further Information ...................................................................................................................................... 6-1

Revision History

Section II. iCE40LM Family Data Sheet

Introduction

General Description ........................................................................................................................................... 8-1

Features ............................................................................................................................................................. 8-1

Applications........................................................................................................................................................ 8-1

Introduction ........................................................................................................................................................ 8-2

Architecture

Architecture Overview ........................................................................................................................................ 9-1

PLB Blocks................................................................................................................................................ 9-2

Routing...................................................................................................................................................... 9-3

Clock/Control Distribution Network ........................................................................................................... 9-3

sysCLOCK Phase Locked Loops (PLLs) - NOT SUPPORTED on the 25-Pin WLCSP............................ 9-4

sysMEM Embedded Block RAM Memory ................................................................................................. 9-5

sysIO Buffer Banks ................................................................................................................................... 9-7

sysIO Buffer .............................................................................................................................................. 9-8

On-Chip Strobe Generators ...................................................................................................................... 9-9

User I

C IP .............................................................................................................................................. 9-10

User SPI IP ............................................................................................................................................. 9-10

High Drive I/O Pins.................................................................................................................................. 9-10

Power On Reset...................................................................................................................................... 9-10

iCE40LM Configuration .................................................................................................................................... 9-11

Power Saving Options............................................................................................................................. 9-11

DC and Switching Characteristics

Absolute Maximum Ratings ............................................................................................................................. 10-1

Recommended Operating Conditions .............................................................................................................. 10-1

Power Supply Ramp Rates .............................................................................................................................. 10-1

Power-On-Reset Voltage Levels...................................................................................................................... 10-2

Power Up Sequence ........................................................................................................................................ 10-2

ESD Performance ............................................................................................................................................ 10-2

DC Electrical Characteristics............................................................................................................................ 10-2

Supply Current ................................................................................................................................................ 10-3

User I

C Specifications..................................................................................................................................... 10-3

User SPI Specifications.................................................................................................................................... 10-3

sysIO Recommended Operating Conditions.................................................................................................... 10-4

sysIO Single-Ended DC Electrical Characteristics........................................................................................... 10-4

Typical Building Block Function Performance.................................................................................................. 10-4

Pin-to-Pin Performance (LVCMOS25) .................................................................................................... 10-4

Table of Contents

iCE40 LP/HX/LM Family Handbook

Register-to-Register Performance .......................................................................................................... 10-4

Derating Logic Timing ...................................................................................................................................... 10-5

Maximum sysIO Buffer Performance ............................................................................................................... 10-5

iCE40LM Family Timing Adders....................................................................................................................... 10-5

iCE40LM External Switching Characteristics ................................................................................................... 10-6

sysCLOCK PLL Timing – Preliminary .............................................................................................................. 10-7

SPI Master Configuration Time ........................................................................................................................ 10-8

sysCONFIG Port Timing Specifications ........................................................................................................... 10-8

Switching Test Conditions................................................................................................................................ 10-9

Pinout Information

Signal Descriptions .......................................................................................................................................... 11-1

Pin Information Summary................................................................................................................................. 11-3

Ordering Information

iCE40LM Part Number Description .................................................................................................................. 12-1

Ordering Part Numbers .................................................................................................................................... 12-1

Supplemental Information

For Further Information .................................................................................................................................... 13-1

Revision History

Section III. iCE40 LP/HX/LM Family Technical Notes

iCE40 Programming and Configuration

Introduction ...................................................................................................................................................... 15-1

Configuration Overview.................................................................................................................................... 15-1

Configuration Mode Selection .......................................................................................................................... 15-2

Mode Selection for iCE40 LP and iCE40 HX .......................................................................................... 15-2

Mode Selection for iCE40LM .................................................................................................................. 15-4

Nonvolatile Configuration Memory (NVCM) (Applies to iCE40 LP and iCE40 HX Devices Only).................... 15-5

NVCM Programming ............................................................................................................................... 15-5

Configuration Control Signals .......................................................................................................................... 15-5

Internal Oscillator ............................................................................................................................................. 15-6

Internal Device Reset....................................................................................................................................... 15-7

Power-On Reset (POR) .......................................................................................................................... 15-7

CRESET_B Pin ....................................................................................................................................... 15-7

sysCONFIG Port .............................................................................................................................................. 15-8

sysCONFIG Pins.............................................................................................................................................. 15-8

SPI Master Configuration Interface .................................................................................................................. 15-9

SPI PROM Requirements ....................................................................................................................... 15-9

Enabling SPI Configuration Interface .................................................................................................... 15-10

SPI Master Configuration Process ........................................................................................................ 15-10

Cold Boot Configuration Option (Applies to iCE40 LP and iCE40 HX Devices Only) .................................... 15-13

Warm Boot Configuration Option (Applies to iCE40 LP and iCE40 HX Devices Only).................................. 15-14

Time-Out and Retry........................................................................................................................................ 15-14

SPI Slave Configuration Interface .................................................................................................................. 15-14

Enabling SPI Configuration Interface .................................................................................................... 15-15

SPI Slave Configuration Process .......................................................................................................... 15-16

Voltage Compatibility ............................................................................................................................ 15-19

Technical Support Assistance........................................................................................................................ 15-19

Revision History ............................................................................................................................................. 15-20

Appendix A. SPI Slave Configuration Procedure ........................................................................................... 15-21

CPU Configuration Procedure............................................................................................................... 15-21

Configuration Waveforms...................................................................................................................... 15-21

Pseudo Code ........................................................................................................................................ 15-23

Memory Usage Guide for iCE40 Devices

Introduction ...................................................................................................................................................... 16-1

Memories in iCE40 Devices ............................................................................................................................. 16-1

Table of Contents

iCE40 LP/HX/LM Family Handbook

iCE40 sysMEM Embedded Block RAM ........................................................................................................... 16-2

Signals .................................................................................................................................................... 16-3

Timing Diagram....................................................................................................................................... 16-3

Write Operations ..................................................................................................................................... 16-4

Read Operations ..................................................................................................................................... 16-4

EBR Considerations................................................................................................................................ 16-4

iCE40 sysMEM Embedded Block RAM Memory Primitives............................................................................. 16-5

SB_RAM256x16...................................................................................................................................... 16-6

SB_RAM512x8........................................................................................................................................ 16-8

SB_RAM1024x4.................................................................................................................................... 16-10

SB_RAM2048x2.................................................................................................................................... 16-12

SB_RAM40_4K ..................................................................................................................................... 16-14

EBR Utilization Summary in iCEcube2 Design Software ............................................................................... 16-16

Technical Support Assistance........................................................................................................................ 16-17

Revision History ............................................................................................................................................. 16-17

Appendix A. Standard HDL Code References ............................................................................................... 16-18

Single-Port RAM ................................................................................................................................... 16-18

Dual Port Ram....................................................................................................................................... 16-19

iCE40 sysCLOCK PLL Design and Usage Guide

Introduction ...................................................................................................................................................... 17-1

Global Routing Resources ............................................................................................................................... 17-1

Verilog Instantiation................................................................................................................................. 17-2

VHDL Instantiation .................................................................................................................................. 17-2

iCE40 sysCLOCK PLL ..................................................................................................................................... 17-3

iCE40 sysCLOCK PLL Features ............................................................................................................. 17-3

Signals .................................................................................................................................................... 17-4

Clock Input Requirements....................................................................................................................... 17-6

PLL Output Requirements....................................................................................................................... 17-6

Functional Description............................................................................................................................. 17-6

Generating iCE40 PLL Using PLL Module Generator in iceCube2 Design Software ...................................... 17-8

PLL Module Generator Output .............................................................................................................. 17-15

iCEcube2 Design Software Report File................................................................................................. 17-16

Hardware Design Considerations .................................................................................................................. 17-16

PLL Placement Rules............................................................................................................................ 17-16

Analog Power Supply Filter for PLL ...................................................................................................... 17-16

Technical Support Assistance........................................................................................................................ 17-17

Revision History ............................................................................................................................................. 17-17

iCE40 Hardware Checklist

Introduction ...................................................................................................................................................... 18-1

Power Supply ................................................................................................................................................... 18-1

Analog Power Supply Filter for PLL ................................................................................................................. 18-1

Configuration Considerations.................................................................................................................. 18-2

SPI Flash Requirement in Master SPI Mode .......................................................................................... 18-3

LVDS Pin Assignments (For iCE40LP/HX Devices Only)................................................................................ 18-3

Checklist........................................................................................................................................................... 18-3

Technical Support Assistance.......................................................................................................................... 18-4

Revision History ............................................................................................................................................... 18-4

Using Differential I/O



(LVDS, Sub-LVDS)



in iCE40 LP/HX Devices

Introduction ...................................................................................................................................................... 19-1

Differential Outputs .......................................................................................................................................... 19-1

Differential Inputs ............................................................................................................................................. 19-3

LVDS and Sub-LVDS Termination................................................................................................................... 19-3

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