or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1009
Introduction_01.4
Introduction
LatticeXP2 Family Data Sheet
Introduction
LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architec-
ture referred to as flexiFLASH.
The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with
FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live
Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies.
The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low
cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked
Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks.
Lattice Diamond
®
design software allows large and complex designs to be efficiently implemented using the
LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis
tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning tools
to place and route the design in the LatticeXP2 device. The Diamond tool extracts the timing from the routing and
back-annotates it into the design for timing verification.
Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LatticeXP2 family. By
using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
1-2
LatticeXP2 Family Data Sheet
Architecture
March 2014
Data Sheet DS1009
Architecture Overview
Each LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and a row of sys-
DSP™ Digital Signal Processing blocks as shown in Figure 2-1.
On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks.
In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™
peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the con-
figuration SRAM. With this technology, expensive external configuration memory is not required, and designs are
secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via
wide busses happens in microseconds, providing an “instant-on” capability that allows easy interfacing in many
applications. LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory
Blocks at user request.
There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building
blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic
and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be imple-
mented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used
per row.
LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18Kbit
memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addi-
tion, LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumu-
lators, which are the building blocks for complex signal processing capabilities.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the
LatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards.
PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic
also includes pre-engineered support to aid in the implementation of high speed source synchronous standards
such as 7:1 LVDS interfaces, found in many display applications, and memory interfaces including DDR and DDR2.
The LatticeXP2 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is
configured, the device enters into user mode with these registers SET/RESET according to the configuration set-
ting, allowing device entering to a known state for predictable system function.
Other blocks provided include PLLs and configuration functions. The LatticeXP2 architecture provides up to four
General Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device.
The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates
and dual boot support is located between banks two and three. Every device in the LatticeXP2 family supports a
sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided
between banks two and three.
This family also provides an on-chip oscillator. LatticeXP2 devices use 1.2V as their core voltage.
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
[i=s] This post was last edited by pomin on 2022-8-27 19:33 [/i] # [Home Smart Dashboard] Development and Construction of ESP-IDF under Linux > My laptop only has four cores, and compiling IDF is too ...
When studying nboot, there are several puzzles: I want nboot to have the function of copying eboot to RAM, so I need to enter the loadboot function to copy. #if 1 //This function is not used in the Fr...
[b]VC++ implements the extraction of GPS global positioning system positioning data[/b] Abstract: This paper proposes a method for receiving GPS global positioning system positioning information and e...
The index requirements are: input AC voltage 220V (50-60Hz), output DC voltage 5V, output current 3A, when the input AC voltage changes between 180-250V, the relative change of output voltage is less ...
Security concerns of different IoT implementations, from low-power ISM networks like ZigBee and Thread to larger scale Wi-Fi networks. The IoT is growing, with many different wireless technologies and...
[size=4][b]Diodes in series[/b][/size] [size=4] [/size] [size=4]When diodes are used in series, attention must be paid to their static and dynamic voltage balancing. [/size] [align=center][/align][ali...
On August 24th, Tesla CEO Elon
Musk
revealed information about the upcoming FSD V14, claiming it will outperform human drivers. Tesla FSD lead Ashok stated last year that FSD version 12.5, ...[Details]
Electric vehicles are becoming increasingly popular, with increasingly longer ranges. There are two ways to charge electric vehicles: slow charging and fast charging. Which is the most suitable? Sl...[Details]
The complexity of the integrated circuits (ICs) used in electronic systems in vehicles is increasing. They aim to execute artificial intelligence (AI) algorithms to control autonomous driving funct...[Details]
1. Ease of Use: The HMI module should be designed to be simple and clear, allowing users to easily operate and configure the energy storage device.
2. Ease of Maintenance: The HMI module should...[Details]
Based on the commutation technology, thyristor rectifiers are classified into two main types. Line-commutated and force-commutated inverters are commonly used, while other commutated inverters, nam...[Details]
On August 22, according to CNBC's report today, the National Highway Traffic Safety Administration (NHTSA) is launching an investigation into Tesla, and the latter is questioned whether it has fail...[Details]
MQTT Ethernet I/O modules primarily collect I/O port information and transmit data over the network. In addition to being a TCP server, Ethernet I/O modules can also function as TCP clients. Furthe...[Details]
The driving mode is not unfamiliar to vehicles. According to the driving mode of the vehicle, there are front-wheel drive, rear-wheel drive and even four-wheel drive. Four-wheel drive is a major se...[Details]
Consumer demand for premium listening experiences has driven rapid evolution in the wireless headphone market in recent years. Hybrid designs, which utilize two drivers per earbud to enhance sound ...[Details]
I recently read an article in the Wall Street Journal titled "We need the right to repair our gadgets" (reference original article: ). The author was very angry about the phenomenon of "planned obs...[Details]
Lithium-ion batteries are a key component of electric vehicles. Their high energy density enables them to store a large amount of energy in a relatively compact and lightweight package, which is cr...[Details]
summary
Modern cars strive to provide the same comfort and entertainment features found in the home, resulting in explosive growth in demand for electronic control units (ECUs). Howe...[Details]
The characteristics of electric vehicles place high demands on the motors they use. To increase top speed, the motor should have high instantaneous power and power density (W/kg); to increase drivi...[Details]
How do the maps used by self-driving cars differ from the maps we use daily, such as those from AutoNavi and Baidu? AutoNavi and Baidu create maps for humans, while high-precision map companies cre...[Details]
On August 18, Tencent Holdings released its second-quarter 2025 results last week, with revenue of 184.504 billion yuan, a year-on-year increase of 15% and a month-on-month increase of 2%; profit a...[Details]
DigiKey Technology Zone
京公网安备 11010802033920号
EEWORLD
