DS80C320/DS80C323
High-Speed/Low-Power Microcontrollers
www.maxim-ic.com
FEATURES
80C32-Compatible
8051 Pin and Instruction Set Compatible
Four 8-Bit I/O Ports
Three 16-Bit Timer/Counters
256 Bytes Scratchpad RAM
Addresses 64kB ROM and 64kB RAM
High-Speed Architecture
4 Clocks/Machine Cycle (8032 = 12)
DC to 33MHz (DS80C320)
DC to 18MHz (DS80C323)
Single-Cycle Instruction in 121ns
Uses Less Power for Equivalent Work
Dual Data Pointer
Optional Variable Length MOVX to Access
Fast/Slow RAM/Peripherals
High-Integration Controller Includes:
Power-Fail Reset
Programmable Watchdog Timer
Early Warning Power-Fail Interrupt
Two Full-Duplex Hardware Serial Ports
13 Total Interrupt Sources with Six
External
Available in 40-Pin DIP, 44-Pin PLCC, and
44-Pin TQFP
PIN CONFIGURATIONS
TOP VIEW
The
High-Speed Microcontroller User’s Guide
must be
used in conjunction with this data sheet.
Download it
at:
www.maxim-ic.com/microcontrollers.
Data sheets contain pin descriptions, feature
overviews, and electrical specifications, whereas the
user’s guide contains detailed information about
device features and operation.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 101006
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
DETAILED DESCRIPTION
The DS80C320/DS80C323 are fast 80C31/80C32-compatible microcontrollers. Wasted clock and
memory cycles have been removed using a redesigned processor core. As a result, every 8051 instruction
is executed between 1.5 and 3 times faster than the original for the same crystal speed. Typical
applications see a speed improvement of 2.5 times using the same code and same crystal. The DS80C320
offers a maximum crystal rate of 33MHz, resulting in apparent execution speeds of 82.5MHz
(approximately 2.5X).
The DS80C320/DS80C323 are pin compatible with all three packages of the standard 80C32 and offer
the same timer/counters, serial port, and I/O ports. In short, the devices are extremely familiar to 8051
users, but provide the speed of a 16-bit processor.
The DS80C320 provides several extras in addition to greater speed. These include a second full hardware
serial port, seven additional interrupts, programmable watchdog timer, power-fail interrupt and reset. The
device also provides dual data pointers (DPTRs) to speed block data memory moves. It can also adjust the
speed of off-chip data memory access to between two and nine machine cycles for flexibility in selecting
memory and peripherals.
The DS80C320 operating voltage ranges from 4.25V to 5.5V, making it ideal as a high-performance
upgrade to existing 5V systems. For applications in which power consumption is critical, the DS80C323
offers the same feature set as the DS80C320, but with 2.7V to 5.5V operation.
Designers must have two documents to fully use all the features of this device: this data sheet and the
High-Speed
Microcontroller
User’s
Guide,
available
on
our
website
at
www.maxim-ic.com/microcontrollers.
Data sheets contain pin descriptions, feature overviews, and
electrical specifications, whereas our user’s guides contain detailed information about device features and
operation.
ORDERING INFORMATION
PART
DS80C320-MCG
DS80C320-QCG
DS80C320-ECG
DS80C320-MNG
DS80C320-QNG
DS80C320-ENG
DS80C320-MCL
DS80C320-QCL
DS80C320-ECL
DS80C320-MNL
DS80C320-QNL
DS80C320-ENL
DS80C323-MCD
DS80C323-QCD
DS80C323-ECD
DS80C323-QND
DS80C323-END
Pb-FREE/RoHS-
COMPLIANT
DS80C320-MCG+
DS80C320-QCG+
DS80C320-ECG+
DS80C320-MNG+
DS80C320-QNG+
DS80C320-ENG+
DS80C320-MCL+
DS80C320-QCL+
DS80C320-ECL+
DS80C320-MNL+
DS80C320-QNL+
DS80C320-ENL+
DS80C323-MCD+
DS80C323-QCD+
DS80C323-ECD+
DS80C323-QND+
DS80C323-END+
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
MAX CLOCK
SPEED (MHz)
25
25
25
25
25
25
33
33
33
33
33
33
18
18
18
18
18
PIN-PACKAGE
40 Plastic DIP
44 PLCC
44 TQFP
40 Plastic DIP
44 PLCC
44 TQFP
40 Plastic DIP
44 PLCC
44 TQFP
40 Plastic DIP
44 PLCC
44 TQFP
40 Plastic DIP
44 PLCC
44 TQFP
44 PLCC
44 TQFP
+
Denotes a lead(Pb)-free/RoHS-compliant device.
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DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
Figure 1. Block Diagram
DS80C320/
DS80C323
PIN DESCRIPTION
PIN
NAME
DIP
40
20
PLCC
44
22, 23
FUNCTION
+5V (+3V for DS80C323)
Digital Circuit Ground
Reset Input.
The RST input pin contains a Schmitt voltage input to
recognize external active-high reset inputs. The pin also employs an
internal pulldown resistor to allow for a combination of wired OR
external reset sources. An RC is
not
required for power-up, as the device
provides this function internally.
Crystal Oscillator Pins.
XTAL1 and XTAL2 provide support for
parallel-resonant, AT-cut crystals. XTAL1 acts also as an input in the
event that an external clock source is used in place of a crystal. XTAL2
serves as the output of the crystal amplifier.
Program Store-Enable Output, Active Low.
This signal is commonly
connected to external ROM memory as a chip enable.
PSEN
provides an
active-low pulse width of 2.25 XTAL1 cycles with a period of four
XTAL1 cycles.
PSEN
is driven high when data memory (RAM) is being
accessed through the bus and during a reset condition.
TQFP
38
16, 17
V
CC
GND
9
10
4
RST
18
19
20
21
14
15
XTAL2
XTAL1
29
32
26
PSEN
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DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
PIN DESCRIPTION (continued)
PIN
DIP
PLCC
TQFP
NAME
FUNCTION
Address Latch-Enable Output.
This pin functions as a clock to latch
the external address LSB from the multiplexed address/data bus. This
signal is commonly connected to the latch enable of an external 373
family transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles
and a period of four XTAL1 cycles. ALE is forced high when the
device is in a reset condition.
Port 0, Input/Output.
Port 0 is the multiplexed address/data bus.
During the time when ALE is high, the LSB of a memory address is
presented. When ALE falls, the port transitions to a bidirectional data
bus. This bus is used to read external ROM and read/write external
RAM memory or peripherals. The Port 0 has no true port latch and
cannot be written directly by software. The reset condition of Port 0 is
high. No pullup resistors are needed.
Port 1, I/O.
Port 1 functions as both an 8-bit, bidirectional I/O port and
an alternate functional interface for Timer 2 I/O, new External
Interrupts, and new Serial Port 1. The reset condition of Port 1 is with
all bits at logic 1. In this state, a weak pullup holds the port high. This
condition also serves as an input mode, since any external circuit that
writes to the port will overcome the weak pullup. When software writes
a 0 to any port pin, the device will activate a strong pulldown that
remains on until either a 1 is written or a reset occurs. Writing a 1 after
the port has been at 0 will cause a strong transition driver to turn on,
followed by a weaker sustaining pullup. Once the momentary strong
driver turns off, the port once again becomes the output high (and
input) state. The alternate modes of Port 1 are outlined as follows:
30
33
27
ALE
39
38
37
36
35
34
33
32
43
42
41
40
39
38
37
36
37
36
35
34
33
32
31
30
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
1–8
2–9
40–44,
1–3
PIN
P1.0–P1.7
DIP
PLCC
TQFP
PORT
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
ALTERNATE
T2
T2EX
RXD1
TXD1
INT2
INT3
INT4
INT5
FUNCTION
External I/O for
Timer/Counter 2
Timer/Counter 2
Capture/Reload Trigger
Serial Port 1 Input
Serial Port 1 Output
External Interrupt 2
(Positive-Edge Detect)
External Interrupt 3
(Negative-Edge Detect)
External Interrupt 4
(Positive-Edge Detect)
External Interrupt 5
(Negative-Edge Detect)
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
40
41
42
43
44
1
2
3
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DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
PIN DESCRIPTION (continued)
DIP
21
22
23
24
25
26
27
28
PIN
PLCC
24
25
26
27
28
29
30
31
TQFP
18
19
20
21
22
23
24
25
NAME
A8 (P2.0)
A9 (P2.1)
A10 (P2.2)
A11 (P2.3)
A12 (P2.4)
A13 (P2.5)
A14 (P2.6)
A15 (P2.7)
FUNCTION
Port 2, Output.
Port 2 serves as the MSB for external addressing.
P2.7 is A15 and P2.0 is A8. The device will automatically place the
MSB of an address on P2 for external ROM and RAM access.
Although Port 2 can be accessed like an ordinary I/O port, the value
stored on the Port 2 latch will never be seen on the pins (due to
memory access). Therefore, writing to Port 2 in software is only
useful for the instructions MOVX A, @Ri or MOVX @Ri, A. These
instructions use the Port 2 internal latch to supply the external address
MSB. In this case, the Port 2 latch value will be supplied as the
address information.
Port 3, Input/Output.
Port 3 functions as both an 8-bit, bidirectional
I/O port and an alternate functional interface for External Interrupts,
Serial Port 0, Timer 0 & 1 Inputs,
RD
and
WR
strobes. The reset
condition of Port 3 is with all bits at logic 1. In this state, a weak
pullup holds the port high. This condition also serves as an input
mode, since any external circuit that writes to the port will overcome
the weak pullup. When software writes a 0 to any port pin, the device
will activate a strong pulldown that remains on until either a 1 is
written or a reset occurs. Writing a 1 after the port has been at 0 will
cause a strong transition driver to turn on, followed by a weaker
sustaining pullup. Once the momentary strong driver turns off, the
port once again becomes both the output high and input state. The
alternate modes of Port 3 are outlined below:
PIN
DIP
PLCC
TQFP
10–17
11, 13–
19
PORT
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
ALTERNATE
RXD0
TXD0
INT0
INT1
MODE
Serial Port 0 Input
Serial Port 0 Output
External Interrupt 0
External Interrupt 1
Timer 0 External Input
Timer 1 External Input
External Data Memory Write
Strobe
External Data Memory Read
Strobe
5, 7–13
P3.0–P3.7
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
T0
T1
WR
RD
31
35
12, 34,
1*
29
6, 28,
39*
EA
External Access, Active-Low Input.
This pin must be connected to
ground for proper operation.
No Connection (Reserved).
These pins should not be connected.
They are reserved for use with future devices in this family.
*These
pins are reserved for additional ground pins on future products.
—
N.C.
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