or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit
SERDES, and 8-bit SERDES modes
• Data Rates 230 Mbps to 3.2 Gbps per channel
for all other protocols
• Up to 16 channels per device: PCI Express,
SONET/SDH, Ethernet (1GbE, SGMII, XAUI),
CPRI, SMPTE 3G and Serial RapidIO
• Fully cascadable slice architecture
• 12 to 160 slices for high performance multiply
and accumulate
• Powerful 54-bit ALU operations
• Time Division Multiplexing MAC Sharing
• Rounding and truncation
• Each slice supports
– Half 36x36, two 18x18 or four 9x9 multipliers
– Advanced 18x36 MAC and 18x18 Multiply-
Multiply-Accumulate (MMAC) operations
• Up to 6.85Mbits sysMEM™ Embedded Block
RAM (EBR)
• 36K to 303K bits distributed RAM
• Two DLLs and up to ten PLLs per device
Embedded SERDES
• Dedicated read/write levelling functionality
• Dedicated gearing logic
• Source synchronous standards support
– ADC/DAC, 7:1 LVDS, XGMII
– High Speed ADC/DAC devices
• Dedicated DDR/DDR2/DDR3 memory with DQS
support
• Optional Inter-Symbol Interference (ISI)
correction on outputs
Programmable sysI/O™ Buffer Supports
Wide Range of Interfaces
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
On-chip termination
Optional equalization filter on inputs
LVTTL and LVCMOS 33/25/18/15/12
SSTL 33/25/18/15 I, II
HSTL15 I and HSTL18 I, II
PCI and Differential HSTL, SSTL
LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
Flexible Device Configuration
Dedicated bank for configuration I/Os
SPI boot flash interface
Dual-boot images supported
Slave SPI
TransFR™ I/O for simple field updates
Soft Error Detect embedded macro
System Level Support
IEEE 1149.1 and IEEE 1532 compliant
Reveal Logic Analyzer
ORCAstra FPGA configuration utility
On-chip oscillator for initialization & general use
1.2V core power supply
ECP3-35
33
72
ECP3-70
67
240
ECP3-95
92
240
ECP3-150
149
372
700
36
1
24
1327
68
1
64
4420
145
3
128
4420
188
3
128
6850
303
4
320
2/2
4/2
10 / 2
10 / 2
10 / 2
4 / 133
4 / 295
4 / 310
4 / 295
8 / 380
12 / 490
4 / 295
8 / 380
12 / 490
8 / 380
16 / 586
1-1
DS1021
Introduction_01.3
Lattice Semiconductor
Introduction
LatticeECP3 Family Data Sheet
Introduction
The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor-
mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous
interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture
and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.
The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to
486 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel
I/O standards.
The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad
range of interface standards, including DDR3, XGMII and 7:1 LVDS.
The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler-
ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular
data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha-
sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various
forms of media.
The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa-
bility, bit-stream encryption, and TransFR field upgrade features.
The ispLEVER
®
design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeECP3 device. The ispLEVER tool extracts the timing from the routing and back-
annotates it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP3
family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the
unique aspects of their design, increasing their productivity.
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1-2
The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices
utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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