EP1C20F400C7N datasheet, PDF - EEWORLD Datasheet

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EP1C20F400C7N: Descriptionfpga - field programmable gate array fpga - cyclone I 2006 labs 301 ios; CategoryProgrammable logic devices Programmable logic; File Size2MB，385 Pages; ManufacturerAltera (Intel); Environmental Compliance

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fpga - field programmable gate array fpga - cyclone I 2006 labs 301 ios

EP1C20F400C7N Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	21 X 21 MM, 1.00 MM PITCH, FBGA-400
Contacts	400
Reach Compliance Code	unknow
ECCN code	3A991
maximum clock frequency	320 MHz
JESD-30 code	S-PBGA-B400
JESD-609 code	e1
length	21 mm
Humidity sensitivity level	3
Configurable number of logic blocks	20060
Number of entries	301
Number of logical units	20060
Output times	301
Number of terminals	400
Maximum operating temperature	85 °C
Minimum operating temperature
organize	20060 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA400,20X20,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
power supply	1.5,1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.2 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	21 mm

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Cyclone Device Handbook, Volume 1

Preliminary Information

101 Innovation Drive

San Jose, CA 95134

www.altera.com

C5V1-2.4

Contents

Chapter Revision Dates ........................................................................... xi

About this Handbook ............................................................................. xiii

How to Find Information ..................................................................................................................... xiii

How to Contact Altera .......................................................................................................................... xiii

Typographic Conventions .................................................................................................................... xiv

Section I. Cyclone FPGA Family Data Sheet

Revision History .................................................................................................................................... 2–1

Chapter 1. Introduction

Introduction ............................................................................................................................................ 1–1

Features ................................................................................................................................................... 1–1

Document Revision History ................................................................................................................. 1–3

Chapter 2. Cyclone Architecture

Functional Description .......................................................................................................................... 2–1

Logic Array Blocks ................................................................................................................................ 2–3

LAB Interconnects ............................................................................................................................ 2–3

LAB Control Signals ......................................................................................................................... 2–4

Logic Elements ....................................................................................................................................... 2–5

LUT Chain and Register Chain ...................................................................................................... 2–7

addnsub Signal ................................................................................................................................. 2–7

LE Operating Modes ........................................................................................................................ 2–7

MultiTrack Interconnect ..................................................................................................................... 2–12

Embedded Memory ............................................................................................................................. 2–18

Memory Modes ............................................................................................................................... 2–18

Parity Bit Support ........................................................................................................................... 2–20

Shift Register Support .................................................................................................................... 2–20

Memory Configuration Sizes ........................................................................................................ 2–21

Byte Enables .................................................................................................................................... 2–23

Control Signals and M4K Interface .............................................................................................. 2–23

Independent Clock Mode .............................................................................................................. 2–25

Input/Output Clock Mode ........................................................................................................... 2–25

Read/Write Clock Mode ............................................................................................................... 2–28

Single-Port Mode ............................................................................................................................ 2–29

Global Clock Network and Phase-Locked Loops ........................................................................... 2–29

Global Clock Network ................................................................................................................... 2–29

Altera Corporation

iii

Preliminary

Cyclone Device Handbook, Volume 1

Dual-Purpose Clock Pins .............................................................................................................. 2–31

Combined Resources ..................................................................................................................... 2–31

PLLs .................................................................................................................................................. 2–32

Clock Multiplication and Division .............................................................................................. 2–35

External Clock Inputs .................................................................................................................... 2–36

External Clock Outputs ................................................................................................................. 2–36

Clock Feedback ............................................................................................................................... 2–37

Phase Shifting ................................................................................................................................. 2–37

Lock Detect Signal .......................................................................................................................... 2–37

Programmable Duty Cycle ........................................................................................................... 2–38

Control Signals ................................................................................................................................ 2–38

I/O Structure ........................................................................................................................................ 2–39

External RAM Interfacing ............................................................................................................. 2–46

DDR SDRAM and FCRAM ........................................................................................................... 2–46

Programmable Drive Strength ..................................................................................................... 2–49

Open-Drain Output ........................................................................................................................ 2–50

Slew-Rate Control .......................................................................................................................... 2–51

Bus Hold .......................................................................................................................................... 2–51

Programmable Pull-Up Resistor .................................................................................................. 2–51

Advanced I/O Standard Support ................................................................................................ 2–52

LVDS I/O Pins ................................................................................................................................ 2–54

MultiVolt I/O Interface ................................................................................................................. 2–54

Power Sequencing and Hot Socketing ............................................................................................. 2–55

Referenced Documents ....................................................................................................................... 2–56

Document Revision History ............................................................................................................... 2–56

Chapter 3. Configuration and Testing

IEEE Std. 1149.1 (JTAG) Boundary Scan Support .............................................................................

SignalTap II Embedded Logic Analyzer ............................................................................................

Configuration .........................................................................................................................................

Operating Modes ..............................................................................................................................

Configuration Schemes ...................................................................................................................

Referenced Documents .........................................................................................................................

Document Revision History .................................................................................................................

3–1

3–5

3–6

3–7

Chapter 4. DC and Switching Characteristics

Operating Conditions ........................................................................................................................... 4–1

Power Consumption ............................................................................................................................. 4–8

Timing Model ......................................................................................................................................... 4–9

Preliminary and Final Timing ........................................................................................................ 4–9

Performance .................................................................................................................................... 4–10

Internal Timing Parameters .......................................................................................................... 4–11

External Timing Parameters ......................................................................................................... 4–15

External I/O Delay Parameters .................................................................................................... 4–21

Maximum Input and Output Clock Rates .................................................................................. 4–27

PLL Timing ...................................................................................................................................... 4–29

Referenced Document ......................................................................................................................... 4–31

Preliminary

Altera Corporation

Contents

Document Revision History ............................................................................................................... 4–31

Chapter 5. Reference and Ordering Information

Software ..................................................................................................................................................

Device Pin-Outs .....................................................................................................................................

Ordering Information ...........................................................................................................................

Referenced Documents .........................................................................................................................

Document Revision History .................................................................................................................

5–1

5–2

Section II. Clock Management

Revision History .................................................................................................................................... 5–1

Chapter 6. Using PLLs in Cyclone Devices

Introduction ............................................................................................................................................ 6–1

Hardware Overview ........................................................................................................................ 6–1

Software Overview .......................................................................................................................... 6–4

Pins and Clock Network Connections .......................................................................................... 6–6

Hardware Features ................................................................................................................................ 6–8

Clock Multiplication and Division ................................................................................................ 6–8

Phase Shifting ................................................................................................................................... 6–9

Programmable Duty Cycle ........................................................................................................... 6–10

External Clock Output ................................................................................................................... 6–11

Control Signals ................................................................................................................................ 6–12

Clock Feedback Modes ....................................................................................................................... 6–13

Normal Mode .................................................................................................................................. 6–14

Zero Delay Buffer Mode ................................................................................................................ 6–15

No Compensation .......................................................................................................................... 6–15

Pins ......................................................................................................................................................... 6–16

Board Layout ........................................................................................................................................ 6–17

VCCA and GNDA .......................................................................................................................... 6–17

Jitter Considerations ...................................................................................................................... 6–19

Specifications ........................................................................................................................................ 6–20

Software Support ................................................................................................................................. 6–20

Quartus II altpll Megafunction ..................................................................................................... 6–20

altpll Input Ports ............................................................................................................................. 6–22

altpll Output Ports ......................................................................................................................... 6–23

MegaWizard Customization ......................................................................................................... 6–23

MegaWizard Page Description ..................................................................................................... 6–25

Compilation Report ....................................................................................................................... 6–31

Timing Analysis .............................................................................................................................. 6–33

Simulation ....................................................................................................................................... 6–37

Global Clock Network ........................................................................................................................ 6–38

Dedicated Clock Input Pins .......................................................................................................... 6–40

Dual-Purpose Clock I/O Pins ...................................................................................................... 6–40

Combined Sources .......................................................................................................................... 6–41

Altera Corporation

Preliminary

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