or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1020_23.1
Lattice Semiconductor
Table 2. ispMACH 4000Z Family Selection Guide
ispMACH 4032ZC
Macrocells
I/O + Dedicated Inputs
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
f
MAX
(MHz)
Supply Voltage (V)
Max. Standby Icc (µA)
Pins/Package
32
32+4/32+4
3.5
2.2
3.0
267
1.8
20
48 TQFP
56 csBGA
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4064ZC
64
32+4/32+12/
64+10/64+10
3.7
2.5
3.2
250
1.8
25
48 TQFP
56 csBGA
100 TQFP
132 csBGA
ispMACH 4128ZC
128
64+10/96+4
4.2
2.7
3.5
220
1.8
35
ispMACH 4256ZC
256
64+10/96+6/
128+4
4.5
2.9
3.8
200
1.8
55
100 TQFP
132csBGA
100 TQFP
132 csBGA
176 TQFP
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI
®
2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low
power in a flexible CPLD family.
The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages
ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key
parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH
4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up
resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/
2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary
scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK,
TMS, TDI and TDO are referenced to V
CC
(logic core).
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.
2
Lattice Semiconductor
Figure 1. Functional Block Diagram
CLK0/I
CLK1/I
CLK2/I
CLK3/I
V
CCO0
GND
ispMACH 4000V/B/C/Z Family Data Sheet
I/O
Block
ORP
I/O Bank 0
16
Global Routing Pool
Generic
Logic
Block
16
36
16
36
Generic
16
Logic
Block
I/O
Block
ORP
I/O Bank 1
I/O
Block
ORP
16
Generic
Logic
Block
16
36
16
36
Generic
16
Logic
Block
I/O
Block
ORP
The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can
support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-
patible with the power supply provided to the bank. Support for a variety of standards helps designers implement
designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is con-
nected to V
CCO
of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
ispMACH 4000 Architecture
There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has
36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be
connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still
must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and
predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-
ated I/O cells in the I/O block.
Generic Logic Block
The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock
generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-
pled from macrocells through the ORP. Figure 2 illustrates the GLB.
3
V
CCO1
GND
GOE0
GOE1
V
CC
GND
TCK
TMS
TDI
TDO
Lattice Semiconductor
Figure 2. Generic Logic Block
CLK0
CLK1
CLK2
CLK3
ispMACH 4000V/B/C/Z Family Data Sheet
To GRP
Clock
Generator
1+OE
16 MC Feedback Signals
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
To ORP
To
Product Term
Output Enable
Sharing
Logic Allocator
36 Inputs
from GRP
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
AND Array
36 Inputs,
83 Product Terms
4
16 Macrocells
Lattice Semiconductor
Figure 3. AND Array
In[0]
In[34]
In[35]
ispMACH 4000V/B/C/Z Family Data Sheet
PT0
PT1
PT2
PT3
PT4
Cluster 0
PT75
PT76
PT77
Cluster 15
PT78
PT79
PT80 Shared PT Clock
PT81 Shared PT Initialization
PT82 Shared PTOE
Note:
Indicates programmable fuse.
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms.
The software automatically considers the availability and distribution of product term clusters as it fits the functions
within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed
Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for
increased performance.
The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
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FPGA/CPLD
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