ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services
.
ii
Altera Corporation
Contents
Chapter Revision Dates .......................................................................... vii
About This Handbook .............................................................................. ix
How to Find Information ........................................................................................................................ ix
How to Contact Altera ............................................................................................................................. ix
Typographic Conventions ........................................................................................................................ x
Section I. Stratix Device Family Data Sheet
Revision History ............................................................................................................................ Part I–1
Features ................................................................................................................................................... 1–2
LAB Control Signals ......................................................................................................................... 2–5
Logic Elements ....................................................................................................................................... 2–6
Fast PLLs ........................................................................................................................................ 2–100
Slew-Rate Control ........................................................................................................................ 2–120
Bus Hold ........................................................................................................................................ 2–121
Power Consumption ........................................................................................................................... 4–17
Timing Model ....................................................................................................................................... 4–19
Preliminary & Final Timing .......................................................................................................... 4–19
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FPGA/CPLD
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