Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08GW64
Rev. 3, 1/2011
MC9S08GW64 Series
Covers: MC9S08GW64 and
MC9S08GW32
8-Bit HCS08 Central Processor Unit (CPU)
MC9S08GW64
80-LQFP
Case 917A
14
14
64-LQFP
Case 840F
10
10
comparator can be used as hardware breakpoint. Full mode,
Comparator A compares address and Comparator B compares data.
Supports both tag and force breakpoints
Peripherals
– New version of S08 core with same performace as traditional S08 and
lower power
– Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10 MHz CPU at 3.6 V
to 1.8 V, across temperature range of –40
C
to 85
C
– HC08 instruction set with added BGND instruction
– Support for up to 48 interrupt/reset sources
On-Chip Memory
– Flash read/program/erase over full operating voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and flash
contents
Power-Saving Modes
– Two low power stop modes and reduced power wait mode
– Low power run and wait modes allow peripherals to run while voltage
regulator is in standby
– Peripheral clock gating register can disable clocks to unused modules,
thereby reducing currents
– Very low power external oscillator that can be used in stop2 or stop3
modes to provide accurate clock source to real time counter
– 6
s
typical wakeup time from stop3 mode
Clock Source Options
– Oscillator (XOSC1) — Loop-control Pierce oscillator; Crystal or
ceramic resonator of 32.768 kHz; Clock source for iRTC or ICS
– Oscillator (XOSC2) — Loop-control Pierce oscillator; Crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz;
optional clock source for ICS
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal or
external reference (XOSC1, XOSC2); precision trimming of internal
reference allows 0.2% resolution and 2% deviation over temperature
and voltage; supporting CPU/bus frequencies from 1 MHz to 20 MHz
System Protection
– Watchdog computer operating properly (COP) reset with option to run
from dedicated 1 kHz internal clock source or bus clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode and illegal address detection with reset
– Flash block protection
Development Support
–
LCD
— up to 440 or 836 LCD driver with internal charge pump and
option to provide an internally regulated LCD reference that can be
trimmed for contrast control
–
ADC16
— two analog-to-digital converters; 16-bit resolution; one
dedicated differential per ADC; up to 16-ch; up to 2.5
s
conversion
time for 12-bit mode; automatic compare function; hardware
averaging; calibration registers; temperature sensor; internal bandgap
reference channel; operation in stop3; fully functional from 3.6 V to
1.8 V
–
PRACMP
—three rail to rail programmable reference analog
comparator; up to 8 inputs; on-chip programmable reference generator
output; selectable interrupt on rising, falling, or either edge of
comparator output; operation in stop3
–
SCI
— four full duplex non-return to zero (NRZ); LIN master extended
break generation; LIN slave extended break detection; wakeup on
active edge; SCI0 designed for AMR operation; TxD of SCI1 and SCI2
can be modulated with timers and RxD can recieved through
PRACMP;
–
SPI—
three full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first
shifting; SPI0 designed for AMR opeartion
–
IIC
— up to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt driven byte-by-byte
data transfer; supporting broadcast mode and 10-bit addressing;
supporting SM BUS functionality; can wake from stop3
–
FTM
— 2-channel flextimer module; selectable input capture, output
compare, or buffered edge- or center-aligned PWM on each channel
–
IRTC
— independent real-time clock, independent power domain, 32
bytes RAM, 32.768 kHz input clock optional output to ICS, hardware
calendar, hardware compensation due to crystal or temperature
characteristics, tamper detection and indicator
–
PCRC
— 16/32 bit programmable cyclic redundancy check for
high-speed CRC calculation
–
MTIM
— two 8-bit and one 16-bit timers; configurable clock inputs
and interrupt generation on overflow
–
PDB
— programmable delay block; optimized for scheduling ADC
conversions
–
PCNT
— position counter; working in stop3 mode without waking
CPU; can be used to generate waveforms like timer
Input/Output
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus 3 more breakpoints in breakpoint unit)
– Breakpoint (BKPT) debug module containing three comparators (A, B,
and C) with ability to match addresses in 64 KB space. Each
– 57 GPIOs including one output-only pin
– Eight KBI interrupts with selectable polarity
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
Package Options
– 80-pin LQFP, 64-pin LQFP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010-2011. All rights reserved.
Table of Contents
1
2
3
Devices in the MC9S08GW64 Series. . . . . . . . . . . . . . . . . . . .3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .10
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .10
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .12
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .23
3.8 External Oscillator (XOSCVLP) Characteristics . . . . . .26
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .27
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.2 Timer (TPM/FTM) Module Timing . . . . . . . . . .
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Analog Comparator (PRACMP) Electricals . . . . . . . . .
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 VREF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . .
Package Information and Mechanical Drawings . . . . . . . . . .
29
30
31
34
34
39
40
40
41
41
41
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
1
2
Date
5/26/2010
10/29/2010
Initial public release
Description of Changes
Completed all the TBDs.
Updated the voltage output data in the
Table 20.
Changed the classification marking of |I
InT
| to C in the
Table 8.
Updated
Table 7.
3
1/28/2011
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08GW64RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
2
Freescale Semiconductor
Devices in the MC9S08GW64 Series
V
DDA
/V
SSA
V
REFH
/V
REFL
V
DDA
/V
SSA
V
REFH
/V
REFL
AD[15]
ADC1
V
DDA/
V
SSA
V
REFH
/V
REFL
AD[15]
ADC0
Port A,F,G,H:
AD[15:2]
DADP/M[1]
trig[1]
sel[1]
KBI
trig[0]
sel[0]
Port A,F,G,H:
AD[15:2]
DADP/M[0]
Port B, D:
KBIP[7:0]
2-Channel FTM
Port A, C, F:
FTMCH[0:1]
FTMCLK
16-bit MTIM3
Port A, F:
MTIMCLK
Port B
Port A
PDB
trig[1:0]
sel[1:0]
Port A:
EXTRIG
PTA0/MOSI2/PCNTCH0/SCL/AD2
PTA1/MISO2/PCNTCH1/SDA/AD3
PTA2/SCLK2/FTMCH0/PCNT0/CMPP0
PTA3/SS2/FTMCH1/PCNT1/CMPP1
PTA4/MTIMCLK/RxD2/PCNT2/CMPP2
PTA5/FTMCLK/TxD2/EXTRIG/IRQ
PTA6/CMPOUT0/CLKOUT/BKGD/MS
PTB0/KBIP0/TxD1/EXTAL2
PTB1/KBIP1/RxD1/XTAL2
PTB2/KBIP2/MOSI0/MISO0/RxD0
PTB3/KBIP3/MISO0/MOSI0/TxD0
PTB4/KBIP4/SCLK0/SCL
PTB5/KBIP5/SS0/SDA
PTB6/KBIP6/RxD2/LCD0
PTB7/KBIP7/TxD2/LCD1
PTC0/MOSI1/LCD2
PTC1/MISO1/LCD3
PTC2/SCLK1/LCD4
PTC3/SS1/LCD5
PTC4/FTMCH0/RxD1/LCD6
PTC5/FTMCH1/TxD1/LCD7
PTC6/PCNTCH0/RxD3/LCD8
PTC7/PCNTCH1/TxD3/LCD9
PTD0/KBIP0/MOSI2/LCD10
PTD1/KBIP1/MISO2/LCD11
PTD2/KBIP2/SCLK2/LCD12
PTD3/KBIP3/SS2/LCD13
PTD4/KBIP4/LCD14
PTD5/KBIP5/CLKOUT/LCD15
PTD6/KBIP6/LCD16
PTD7/KBIP7/LCD17
PTE0/LCD18
PTE1/LCD19
PTE2/LCD20
PTE3/LCD21
PTE4/LCD22
PTE5/LCD23
PTE6/LCD24
PTE7/LCD25
PTF0/LCD26
PTF1/LCD27
PTF2/LCD28
PTF3/LCD29
PTF4/LCD30
PTF5/LCD31
PTF6/MTIMCLK/AD4/LCD32
PTF7/FTMCLK/AD5/LCD33
PTG0/MOSI1/AD6/LCD34
PTG1/MISO1/AD7/LCD35
PTG2/SCLK1/AD8/LCD36
PTG3/SS1/AD9/LCD37
PTG4/CMPOUT1/RxD3/AD10/LCD38
PTG5/CMPOUT2/TxD3/AD11/LCD39
PTG6/CMPP3/AD12/PCNT0/LCD40
PTG7/CMPP4/AD13/PCNT1/LCD41
PTH0/CMPP5/AD14/PCNT2/LCD42
PTH1/RTCCLKOUT/CMPP6/AD15/LCD43
V
REFO
V
DD
V
SS1
V
SS2
VREG
8-bit MTIM1
Port A, F:
MTIMCLK
PCRC
8-bit MTIM2
S08 Core V6
CPU
SPI0
Port B:
MOSI0 MISO0
SCLK0 SS0
Port C, G:
MOSI1 MISO1
SCLK1 SS1
Port A, D:
MOSI2 MISO2
SCLK2 SS2
Port A, B:
SDA
SCL
Port B:
RxD0
TxD0
Port B, C:
RxD1
TxD1
Port A, B:
RxD2
TxD2
Port C, G:
RxD3
TxD3
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT0
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT1
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT2
Port H
Port F
Port G
Port D
Port E
BKGD/MS
BKPT
INT
SPI1
SPI2
RESETB
SIM
IIC
COP
LVD
SCI0
FLASH
GW64 64 KB
GW32 32 KB
RAM
GW64 4 KB
GW32 2 KB
Internal Clock Source
REF CLK
IRCLK
PRACMP0
Clock Check & Select
SCI3
SCI1
SCI2
XTAL2
EXTAL2
XTAL1
EXTAL1
V
BAT
TAMPER1
TAMPER2
XOSC2
CLKO
XOSC1
CLKO
PRACMP1
PRACMP2
PCNT
Independent
RTC
The RTC is in a separate
power domain
LCD
Port A, C, G, H:
PCNT0 PCNT1 PCNT2
PCNTCH0 PCNTCH1
Port B, C, D, E, F, G, H:
LCD[0:43]
Figure 1. MC9S08GW64 Series Block Diagram
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
5
Port C
Port A, F:
MTIMCLK
Microcontroller MCU
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