5SGSED8K3F40I3 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > semiconductor> Other integrated circuit (IC)> 5SGSED8K3F40I3

5SGSED8K3F40I3: Descriptionfpga - field programmable gate array stratix V GS; Categorysemiconductor Other integrated circuit (IC); File Size4MB，563 Pages; ManufacturerAltera (Intel); Environmental Compliance

Download Datasheet Parametric Compare View All

5SGSED8K3F40I3 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	5SGSED8K3F40I3	-	-	View	Buy Now

5SGSED8K3F40I3 Overview

fpga - field programmable gate array stratix V GS

5SGSED8K3F40I3 Parametric

Parameter Name	Attribute value
Manufacture	Alte
Product Category	FPGA - Field Programmable Gate Array
RoHS	Yes
Packaging	Tray
Factory Pack Quantity	21

Preview

Download Datasheet

View All

Stratix V Device Handbook

Volume 1: Device Interfaces and Integration

Send Feedback

SV5V1

2015.01.23

101 Innovation Drive

San Jose, CA 95134

www.altera.com

TOC-2

Stratix V Device Handbook Volume 2: Transceivers

Contents

Transceiver Architecture in Stratix V Devices................................................... 1-1

Device Layout............................................................................................................................................... 1-3

Stratix V GX/GT Channel and PCIe Hard IP Layout.................................................................1-4

Stratix V GS Channel and PCIe Hard IP Layout.........................................................................1-5

PMA Architecture........................................................................................................................................1-9

Receiver Buffer............................................................................................................................... 1-10

Receiver Clock Data Recovery Unit............................................................................................ 1-13

Receiver Deserializer..................................................................................................................... 1-15

Transmitter PLLs........................................................................................................................... 1-17

Transmitter Serializer....................................................................................................................1-21

Transmitter Buffer......................................................................................................................... 1-22

Transceiver Calibration Blocks.................................................................................................... 1-24

PMA Reconfiguration................................................................................................................... 1-27

Standard PCS Architecture.......................................................................................................................1-28

Receiver Standard PCS Datapath.................................................................................................1-29

Transmitter Standard PCS Datapath.......................................................................................... 1-42

10G PCS Architecture............................................................................................................................... 1-46

Receiver 10G PCS Datapath......................................................................................................... 1-47

Transmitter 10G PCS Datapath................................................................................................... 1-51

PCIe Gen3 PCS Architecture................................................................................................................... 1-56

Receiver PCIe Gen3 PCS Datapath............................................................................................. 1-57

Transmitter PCIe Gen3 PCS Datapath....................................................................................... 1-59

PIPE Interface.................................................................................................................................1-60

Document Revision History.....................................................................................................................1-60

Transceiver Clocking in Stratix V Devices......................................................... 2-1

Input Reference Clocking........................................................................................................................... 2-1

Input Reference Clock Sources...................................................................................................... 2-1

Internal Clocking......................................................................................................................................... 2-7

Transmitter Clock Network........................................................................................................... 2-8

Transmitter Clocking.................................................................................................................... 2-18

Receiver Clocking.......................................................................................................................... 2-28

FPGA Fabric-Transceiver Interface Clocking....................................................................................... 2-34

Transmitter Datapath Interface Clocking.................................................................................. 2-37

Receiver Datapath Interface Clock ............................................................................................. 2-42

GXB 0 PPM Core Clock Assignment..........................................................................................2-46

Document Revision History.....................................................................................................................2-46

Transceiver Reset Control in Stratix V Devices................................................. 3-1

PHY IP Embedded Reset Controller......................................................................................................... 3-1

Embedded Reset Controller Signals.............................................................................................. 3-2

Altera Corporation

Stratix V Device Handbook Volume 2: Transceivers

TOC-3

Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device

Power-Up.....................................................................................................................................3-3

Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device

Operation.....................................................................................................................................3-4

User-Coded Reset Controller..................................................................................................................... 3-5

User-Coded Reset Controller Signals............................................................................................3-5

Resetting the Transmitter with the User-Coded Reset Controller During Device Power-

Up ................................................................................................................................................ 3-7

Resetting the Transmitter with the User-Coded Reset Controller During Device

Operation.....................................................................................................................................3-8

Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up

Configuration..............................................................................................................................3-9

Resetting the Receiver with the User-Coded Reset Controller During Device Operation

.....................................................................................................................................................3-10

Transceiver Reset Using Avalon Memory Map Registers....................................................................3-11

Transceiver Reset Control Signals Using Avalon Memory Map Registers............................3-11

Clock Data Recovery in Manual Lock Mode......................................................................................... 3-12

Control Settings for CDR Manual Lock Mode.......................................................................... 3-12

Resetting the Transceiver in CDR Manual Lock Mode............................................................3-13

Transceiver Blocks Affected by the Reset and Powerdown Signals....................................................3-14

Document Revision History.....................................................................................................................3-16

Transceiver Configurations in Stratix V Devices............................................... 4-1

Protocols and Transceiver PHY IP Support.............................................................................................4-1

10GBASE-R and 10GBASE-KR................................................................................................................. 4-5

10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration.................................... 4-7

10GBASE-R and 10GBASE-KR Supported Features................................................................4-11

1000BASE-X and 1000BASE-KX Transceiver Datapath..........................................................4-14

1000BASE-X and 1000BASE-KX Supported Features............................................................. 4-14

Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX

Configurations.......................................................................................................................... 4-17

Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX

Configurations.......................................................................................................................... 4-17

Interlaken.................................................................................................................................................... 4-18

Transceiver Datapath Configuration.......................................................................................... 4-18

Supported Features........................................................................................................................ 4-20

Transceiver Clocking.....................................................................................................................4-23

PCI Express (PCIe)—Gen1, Gen2, and Gen3........................................................................................4-24

Transceiver Datapath Configuration.......................................................................................... 4-25

Supported Features for PCIe Configurations............................................................................ 4-28

Supported Features for PCIe Gen3..............................................................................................4-31

Transceiver Clocking and Channel Placement Guidelines......................................................4-34

Advanced Channel Placement Guidelines for PIPE Configurations..................................... 4-42

Transceiver Clocking for PCIe Gen3.......................................................................................... 4-51

XAUI............................................................................................................................................................4-57

Transceiver Datapath in a XAUI Configuration....................................................................... 4-58

Supported Features........................................................................................................................ 4-60

Transceiver Clocking and Channel Placement Guidelines......................................................4-63

Altera Corporation

TOC-4

Stratix V Device Handbook Volume 2: Transceivers

CPRI and OBSAI—Deterministic Latency Protocols...........................................................................4-64

Transceiver Datapath Configuration.......................................................................................... 4-65

Phase Compensation FIFO in Register Mode............................................................................4-66

Channel PLL Feedback..................................................................................................................4-66

CPRI and OBSAI............................................................................................................................4-66

CPRI Enhancements......................................................................................................................4-69

Transceiver Configurations......................................................................................................................4-69

Standard PCS Configurations—Custom Datapath...................................................................4-69

Standard PCS Configurations—Low Latency Datapath.......................................................... 4-75

Transceiver Channel Placement Guidelines.............................................................................. 4-80

10G PCS Configurations...............................................................................................................4-81

Merging Instances..........................................................................................................................4-88

Native PHY IP Configuration.................................................................................................................. 4-89

Native PHY Transceiver Datapath Configuration.................................................................... 4-90

Standard PCS Features.................................................................................................................. 4-91

10G PCS Supported Features....................................................................................................... 4-92

10G Datapath Configurations with Native PHY IP..................................................................4-94

PMA Direct Supported Features..................................................................................................4-97

Channel and PCS Datapath Dynamic Switching Reconfiguration.........................................4-97

Stratix V GT Device Configurations....................................................................................................... 4-97

Document Revision History.....................................................................................................................4-99

Transceiver Loopback Support in Stratix V Devices..........................................5-1

Serial Loopback............................................................................................................................................ 5-1

PIPE Reverse Parallel Loopback................................................................................................................ 5-2

Reverse Serial Loopback..............................................................................................................................5-3

Reverse Serial Pre-CDR Loopback............................................................................................................ 5-4

Document Revision History....................................................................................................................... 5-5

Dynamic Reconfiguration in Stratix V Devices..................................................6-1

Dynamic Reconfiguration Features...........................................................................................................6-1

Offset Cancellation...................................................................................................................................... 6-2

PMA Analog Controls Reconfiguration................................................................................................... 6-2

On-Chip Signal Quality Monitoring (EyeQ)........................................................................................... 6-3

Decision Feedback Equalization................................................................................................................ 6-3

Adaptive Equalization................................................................................................................................. 6-4

Dynamic Reconfiguration of Loopback Modes.......................................................................................6-4

Transceiver PLL Reconfiguration .............................................................................................................6-5

Transceiver Channel Reconfiguration...................................................................................................... 6-5

Transceiver Interface Reconfiguration .................................................................................................... 6-5

Document Revision History....................................................................................................................... 6-6

Altera Corporation

5SGSED8K3F40I3 Related Products

	5SGSED8K3F40I3	5SGXEABN1F45I2	5SGXEA4H3F35I4
Description	fpga - field programmable gate array stratix V GS	fpga - field programmable gate array stratix V GX	fpga - field programmable gate array stratix V GX
Manufacture	Alte	-	Alte
Product Category	FPGA - Field Programmable Gate Array	-	FPGA - Field Programmable Gate Array
RoHS	Yes	-	Yes
Packaging	Tray	-	Tray
Factory Pack Quantity	21	-	24

Recommended Resources

High frequency variable pulse width signal generation circuit

9W audio power amplifier (μPC2002) circuit diagram

CR charge and discharge circuit diagram

High voltage step-down chopper stabilized power supply circuit

FCOG6100 fully functional thyristor trigger circuit

Pulse stretching circuit using a NAND gate

How to Eliminate the Output Offset Error of the MSP4301611 Internal 12-bit DAC Module: The manual says that it can be corrected by controlling the DAC12CALON bit, but in actual use, it is found that there is still an offset error, often a negative offset of about 0.01mv. 1. How can I el...; zhangxiajoa Microcontroller MCU

【GD32450I-EVAL】ADC: software trigger + interrupt + single conversion mode: 1. ADC performance GD32F450 has 3 ADCs, and the sampling speed of each ADC can reach up to 2.6Mpsp, which is still under the condition of 12-bit maximum precision. If the precision is reduced, it can ...; tinnu GD32 MCU

Development of memory chip packaging technology: Abstract This paper mainly introduces the current status and future development of international memory chip packaging technology....; feifei FPGA/CPLD

Master's thesis<>, how to reflect the algorithm?: My friend, Master's thesis, according to the standards of a master's thesis, how to present the algorithm? Please give some advice....; aofa Embedded System

Problems with arm development board and camera~: My question is this: I want to use the arm development board to receive four-way video signals. How can I do this? How can I combine the four cameras (what device should I use?), and then connect them...; alexjoy ARM Technology

How to perform initial performance test on LEM Hall current sensor (soldered on PCB)?: As shown in the figure, the Hall current sensor is a newly purchased part. Please guide me how to conduct the initial function test to prove that the part is qualified. Thank you! !...; zimiaoxinghan Analog electronics

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components